# -*- tcl -*-

# This is used mostly in conjuction with the GDB script.  The idea is
# to put most of the functionality in here, so it can also be used in
# standalone mode (i.e. for test scripts).

# For some reason the "reset init" won't work reliably with a fast
# JTAG clock, so we set a slower clock rate.  Switch to faster rate
# for data transfer commands, i.e. "load" from GDB.

# The AT91SAM7 boots with a 32kHz clock.  What I've found is that it
# doesn't need to be lower than 32kHz (there might be another reason),
# but I definitely get errors when running it above 400kHz.
proc jtag_slow {}  {
    jtag_khz 100
}

# The slowest operation is Flash program, which seems to be limited by
# the speed of the Flash, not the JTAG speed.  So this doesn't need to
# be full throttle. 

# Actually, at 6MHz there seem to be quite some err3ors on the DBB
# board, let's use a slower clock.
proc jtag_fast {}  {
    jtag_khz 1000
}

# Some wrappers for reset commands, slowing down JTAG.
proc slow_reset { kind } {
    jtag_slow
    reset $kind
    jtag_fast
}

## these functions are used in ecos-build/bin/arm-load-start to
## perform load and reset operations such that gdb can just issue
## "continue".
proc app_reset { } {
    slow_reset init
    soft_reset_halt
    #
    # Give a couple of instruction step commands starting from the boot
    # vector.  This is a workaround for a sync problem, avoiding:
    #
    #   stepi ignored. GDB will now fetch the register state from the target.
    #    
    stepi
    stepi
    stepi
}

# This comes from
# /usr/local/share/openocd/scripts/target/at91sam7sx.cfg as the
# commands attached to the reset-init handler.

# Somehow "reset init" doesn't work right on my AT91SAM7S-EK board.
# The first write in the reset-init event triggers the error:
# memory write caused data abort (address: 0xfffffd00, size: 0x4, count: 0x1)



# debug_level 3
debug_level 2

jtag_slow

# Some of these are cargo-cult.  Maybe figure out the minimal setup?
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
gdb_breakpoint_override hard
jtag_nsrst_delay 200
jtag_ntrst_delay 200

# Terminate the configuration stage and enter the run stage.
# http://openocd.berlios.de/doc/html/Daemon-Configuration.html#Configuration%20Stage
init



debug_level 1

# reset init
slow_reset init

# enable DCC console while target is running
target_request debugmsgs charmsg