A grab-bag of electronics circuits, theory recap, hacks and gear nostalgia. Before you trust what is in here, please note that my skills are most developed in the domains of software and general engineering/DSP math. My understanding of electronics theory is reasonably up-to-date, but from the practical design point I lack some experience. These lab notes mostly log the learning experience of designing some (analog) electronic circuits. See also notes about gEDA[1], notes about designing an analog synthesizer[2], ARM microcontroller development[3] and some digital electronics notes dispersed in the Staapl lab notes[4]. [1] entry://../geda [2] entry://../synth [3] entry://../arm [4] entry://../staapl Entry: Elektor Hacks: Symmetric voltages from MAX232 Date: Mon Sep 1 17:23:14 CEST 2008 From Elektor 2008-7/8 (uk version p.57): Gratis Symmetrical Opamp Supply Voltages[1]. This is interesting for analog/digital synth hybrid experiments, since most simple circuits really need a proper symmetric powersupply, and gives a standard serial port interface. Another interesting one on p.125: PR4401/02 off the Beaten Track [1] http://www.elektor.com/magazines/2008/july-047-august/gratis-symmetrical-opamp-supply-voltages.531321.lynkx [2] md5://9aa64ac57203684fd29ed398879fc3c8 Entry: Taking apart the Roland MC-303 Date: Wed Sep 3 16:35:06 CEST 2008 The idea is that I'd like to replace the motherboard with something else, turning the box into a controller, and turn the motherboard into a MIDI sound module. Let's see if the user interface can be cleanly separated from the main board. At first sight it does look like it: there are 2 separate PCBs for the top keyboard panel and the back panel with MIDI+AUDIO IO What follows is what I can figure out just looking at the board. Taking it apart: * remove back and bottom screws. leave the legs alone, they are attached to the bottom plate. * unscrew the mainboard (4 edges) * to remove the PANEL BOARD: disconnect 2 connectors so the mainboard and panel board can be unfolded. * remove knobs + gently pull off the big rotary knob, it is attached to the panel board. DON'T push the buttons with the panel board removed, since this will make the glue come off. also do not remove the dark screen, there's nothing there but glue. On the panel board I count 16 screws in total: 9 that attach to the chassis at the edge, and 7 that attach to a metal part that seems to be glued to the main chassis. Two of those are below the CPU board. Picture 1: Bottom plate removed, all connections intact. Picture 2-3: Jack Board unscrewed and exposed. Picture 4: Main board. JACK BOARD ---------- 74HC04AP hex invertor for midi PC910 optocoupler for midi 4 x C4570C NEC opamp 5218A dual low noise opamp pins con function ------------------ 4 CN5 5 CN6 volume knob (to PANEL BOARD CN3) 9 CN7 digital + power ? (to MOTHER BOARD CN1) PANEL BOARD ----------- 2 x 74HC138AP 3-to-8 Line Decoder 2 x TD62384AP 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER 1 x TD62785P 8CH SOURCE DRIVERS 1 x 74HC245AP Octal bus tranceiver; 3-state pins con function ----------------- 5 CN3 volume knob (to JACK BOARD Cn6) 10 CN4 7x analog rotary knobs, 2 x GND, 1 x KNOB V+ (to MAIN BOARD CN2) 10 CN1 digital (to MAIN BOARD CN4) 12 CN2 digital (to MAIN BOARD CN3) Looks like most buttons have an associated LED. I don't see any load resistors though. Each switch has a diode in series. The source drivers are connected to the line decoders, and to the low end of the switches through a diode. The other end of the switch connects to a pull-up resistor and goes into the tristate. The tristate is also connecteded to the source drivers, which drive the leds into the sink drivers. service manual -------------- That's a lot more convenient: MC-303_SM.pdf from http://www.dtforum.net Looks like i missed the 22R resistors connected to the source drivers. Entry: Obtaining service manuals Date: Wed Sep 3 17:48:01 CEST 2008 http://www.dtforum.net They seem to have a good deal. $12 USD donation gets you one year access. Entry: CANbus Date: Wed Oct 8 02:13:29 CEST 2008 http://en.wikipedia.org/wiki/Canbus Intel i82527 CAN controller. Devices? http://www.testech-elect.com/peaksystem/pcan_pci.htm (82C251) SocketCan (CANbus as sockets: PF_CAN) contributed by VW research. http://en.wikipedia.org/wiki/Socketcan http://developer.berlios.de/projects/socketcan/ CANopen (CAN Festival) http://www.canfestival.org/ (also links to Xenomai) Now, since CAN is only upto 1mbit, why not run it over ethernet? Ether frame overhead (addresss + minimal length) shouldn't matter too much.. Entry: next microchip samples: Date: Sat Oct 18 15:51:33 CEST 2008 ENC28J60 ethernet MCP2552 canbus driver Entry: Legacy busses Date: Sat Oct 18 15:55:22 CEST 2008 ISA: http://upload.wikimedia.org/wikipedia/commons/0/0b/ISA_Bus_pins.png Idea is to get 8 x 1 bit / 1Mbps digital data into the PC. PIC at 40MHz is 10Mips, with one 8 bit port interfaced to an ISA 8bit register, this is probably really at the limit.. Can I use a PIC as an address decoder? For a dedicated PC, maybe it's possible to use a single address bit as chip select, and the remaining as function select? ATA (IDE): derivative of ISA PCMCIA: derivative of ATA COMPACT FLASH: derivative of PCMCIA ISA -> ATA? I didn't know that.. Maybe this can be used for PIC->PC data streaming, since the connectors are quite easy to use. What about PIO 0, 8,3 MB/S 8 bit? Entry: Weller WES51 Date: Fri Dec 26 15:26:32 CET 2008 Got one with 120V US powersupply.. Apparently, the transformer inside is not switchable: 120V/24V, 40VA. Bummer.. Entry: CANbus Date: Sat Jan 17 18:34:21 CET 2009 Electrical: LO HI allowed diff dominant 1.5 3.5 0.9 - 2.0 recessive 2.5 2.5 0.0 - 0.5 This is +-1V differential NRZ signalling. Main ideas of CAN: - communication in noisy environment - arbitration-free broadcast What about re-using networking cable + telephone wire? Local canbus: probably ok to use flatcable + shield? The idea is that CANbus does arbitration, so a local stackable bus on CANbus might be interesting. Does this still need a driver like MCP2551, or can the TX/RX lines be connected? As long as dominant/recessive is respected it should work just fine. Entry: Topcom UBR 624 (S3C2510A + IP175A) Date: Tue Jan 20 13:28:14 CET 2009 cosole IO: AF18 = CUTXD see library/pool/23C2510A.pdf also library/pool/IP175A\ LF-DS-R08-20060220.pdf For the serial port, there is a 2x3-pin header hole underneath one of the 1000uF capacitors, visible from the bottom of the board, with 2 traces running to the microcontroller. 1 GND 2 3 RX 4 TX 5 6 Connecting /dev/ttyUSB1,b19200,raw,echo=0 to - AT Firmware Version = R1.00b7 Command List: IP (set device IP; e.g. IP 192.168.123.254) PW (set new PassWord; e.g. PW admin) DS (toggle Dhcp Server setting) SR (Save new setting and Reboot) RR (Restore default setting and Reboot) SP (set memory address; e.g. SP80000000) OB (set one byte data; e.g. OB) IB (get one byte data; e.g. IB) OW (set two byte data; e.g. OW) IW (get two byte data; e.g. IW) OL (set two byte data; e.g. OL) IL (get two byte data; e.g. IL) RI (get interrupt mask; e.g. RI) SN (show nbuf; e.g. SN) Current Setting: Device IP = 192.168.1.1 DHCP Server = Enable > This[1] is the only google hit I could find, in Japanese. [1] http://pine.zero.ad.jp/meronsoft/mr_pbr007_01.htm Entry: EIA-485 Date: Thu Jan 22 09:45:06 CET 2009 The best solution is probably simple differential signalling over CAT5. This gives raw bit streams, so any protocol can be used (since we want a specific protocol anyway). It can be broken down the following way: - Ethernet/USB <-> EIA-485 : couples microcontroller to PC. - EIA-485 + power <-> TTL serial / SPI. What I really want is probably a linux/xenomai based ARM/POWERPC Ethernet <-> local microcontroller bus coupler. Entry: transceivers MAX3157 Date: Wed Feb 4 20:20:21 CET 2009 They are big. Wide 28-pins PDIP with a whopping 1309 transistors. uC lines: H /F half-full duplex selector TXP transmitter phase RXP receiver phase DE driver output enable DI driver input /RE receiver output enable RO receiver output Entry: profoon ip-22 Date: Mon Feb 16 21:04:29 CET 2009 SN11122APFR Probably related to SN11300 : 3 in 1 USB VoIP Controller http://www.sonix.com.tw/sonix/product.do?p=SN11300 Entry: CANbus over 2-pair telephone wire Date: Thu Apr 2 10:02:02 CEST 2009 2 pair power + CAN blue/purple GND/VCC white/green LO/HI http://www.interfacebus.com/Design_Connector_CAN.html 2 CAN_L white 7 CAN_H green 9 CAN_V+ purple 3 CAN_GND blue Entry: samsung 2333HD Date: Tue Apr 14 15:02:32 CEST 2009 service menu: POWEROFF 1 8 2 POWERON Entry: ninco dvx108 Date: Tue Apr 14 15:43:33 CEST 2009 sunplus 8202R board says: "GW-MPEG(8202R) V2.0 2007/10/18" Entry: Avnet Xilinx Spartan-3A FPGA board Date: Tue May 19 13:50:50 CEST 2009 While neuros system is compiling, let's have a look at the Spartan FPGA board. Board says: SPANSION Cypress PSoC Mixed Signal Arrays Spansion is the flash memory. The cypress PSoC is maybe a microcontroller for the touch pads? Yes, it's connected to CY8C24894-24L which has a PSoC programmer port on J2. PSoC programmer included in a separate package: Cypress CY3217 http://www.cypress.com/shop/?productid=287 The board has a url on the back side: http://www.em.avnet.com/spartan3a-evl Package contains: * Xilinx Spartan-3A evaluation board * ISE WebPACK 10.1 DVD * USB cable * Windows programming application * Now includes: Cypress MiniProg Programming Unit * Downloadable documentation and reference designs Key Features * Xilinx XC3S400A-4FTG256C Spartan-3A FPGA * Four LEDs * Four CapSense switches * I2C temperature sensor * Two 6-pin expansion headers * 20 x 2, 0.1-inch user I/O header * 32 Mb Spansion MirrorBit NOR GL Parallel Flash * 128 Mb Spansion MirrorBit SPI FL Serial Flash * USB-UART bridge * I2C port * SPI and BPI configuration * Xilinx JTAG interface * FPGA configuration via PSoC Supporting Products (BOM): Cypress Semiconductor CY8C24894-24LFXI Cypress PsOC Mixed-Signal Array Maxim MAX7381AXR166-T Maxim 3-pin Silicon Oscillator 16MHz Spansion S25FL128P0XNFI001 32 Mbit SPI Flash Memory Texas Instruments TMP100NA/250 TI Digital Temperature Sensor, I2C Interface TPS3809K33DBVT TI 3-pin Supply Voltage Supervisor, 2.93V Threshold TPS3106K33DBVR TI 3.3V Supply Voltage Supervisor TPS62290DRVT TI 1A Adjustable Step-Down DC-DC Converter SN74CB3T3257PW TI 4-bit 1 of 2 FET Mux/Demux Tpd=250pS SN74AHC1G08DBVR TI Single 2-Input and Gate forum: http://community.em.avnet.com/t5/Spartan-3A-Evaluation-Kit/bd-p/Spartan3A The download page: http://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D46501%2526CAT%253D0%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html?man=Xilinx Xilinx® Spartan®-3A Evaluation Kit App Notes/Ref Designs > Slave Serial Configuration from a Processor > Serial Flash (SPI) Configuration > Parallel Flash (BPI) Configuration ISE Design Suite 10.1 > MicroBlaze Design Introduction > MicroBlaze Parallel Flash Test and Execute in Place > ISE FPGA Design Introduction > MultiBoot in Serial and Parallel Flash > MicroBlaze Serial Flash Test > MicroBlaze IIC Temperature Sensor > MicroBlaze RTOS uC/OS-II Example BOM > Xilinx Spartan-3A Evaluation Kit - BOM Errata > Xilinx Spartan-3A Evaluation Kit - Errata Other > Restoring the Spartan-3A Evaluation Kit to Its Original State > Avnet Programming Utility Install for Windows XP SP3 > Avnet Programming Utility Install for Windowx XP SP2 and Vista > Master User Constraints File (UCF) > Avnet Programming Utility Reference Manual Design Kit Discussion Group > Xilinx Spartan-3A Evaluation Kit Schematics > Xilinx Spartan-3A Evaluation Kit - Schematics > Xilinx Spartan-3A Evaluation Kit - PCB Test Files > Default Serial Flash Factory Image > Factory Test Source Project (EDK 9.2) User Guide > Xilinx Spartan-3A Evaluation Kit - User Guide > Xilinx Spartan-3A Evaluation Kit - Quick Start Guide > Application Programmer Implementation Guide > Xilinx Spartan-3A Evaluation Kit - FAE Field Guide XBD > XBD Files (EDK 9.2i) > XBD Files (EDK 10.1 or later) some more stuff about the board: http://fpgablog.com/posts/avnet-cypress-cy3217-miniprog/ Entry: Atari 1040 STe Date: Mon Jun 8 00:18:58 CEST 2009 MC68901P Multifunction Peripheral MC6850P Async comm YM2149F Sound WD1772 Floppy controller MC68000 CPU MM9092 Blitter C300588 Video shifter LMC1992 Stereo tone and volume Anyways, It doesn't boot with the case on, but with the case removed it works just fine. I tried to exchange some disks with a linux PC without success, to try to get VolksForth[2] to work. Apparently there is now a project to simulate the floppy drive[3]. I closed the box and put it back into storage.. Can't do much with it except stare in awe ;) Apparently the wikipedia page[4] has a description of the chips. [1] http://www.memi.com/niko/studio/Gear/Atari/1040STe/ [2] http://volksforth.sourceforge.net/ [3] http://jeanfrancoisdelnero.free.fr/floppy_drive_emulator/index.html [4] http://en.wikipedia.org/wiki/Atari_ST Entry: Philips VG8020 Date: Mon Jun 8 01:16:11 CEST 2009 This was my first computer. I got a PC and got into C and x86 asm before I ever got serious about Z80 assembler. If I recall it was really hard to get good information. At one time there was a machine code monitor listed in one of the magazines my uncle subscribed to, which was my only source. I keyed it in but couldn't get it to work. A major disappontment which scarred me forever ;) I'd like to set that straight and get Staapl running on the MSX. To bootstrap it, the simplest way is probably the cassette interface: it's FSK to a maximum of 2400 baud. Should be quite easy to hook up to a PC or a simple uC circuit. The cassette tape input connects to the sound chip[3] through an interface circuit consisting of a single opamp configured as a schmitt-trigger. The cassette input is bit7 in register14 of the PSG. After bootstrapping with a standard "bload" format, this could be used directly to read other digital formats. Some more info here[4] and in the MSX Red Book[5]. [1] http://www.funet.fi/pub/msx/docs/service_manuals/philipsvg802000sm.pdf [2] http://msxbanzai.tni.nl/computers/philips.html [3] http://en.wikipedia.org/wiki/YM2149 [4] http://msx.retro8bits.com/msxtape.html [5] http://msx.retro8bits.com/msxarchives/aredbook.zip Entry: Charge pump Date: Wed Jun 10 17:04:22 CEST 2009 A charge pump[1] is a series of diode/capacitor circuits constructed like this: VDD --[>]--+--[>]--+--[>]--+--[>]--+--[>]--+--[>]--+ | | | | | | === C0 === C1 === C2 === C3 === C4 === C5 | | | | | | 1 2 1 2 1 2 It operates by switching the 1 and 2 nodes at opposite voltages. I.e. with 1=VDD and 2=GND, the 1 nodes supply a current that discharges the attached capacitor, goes through the diode and charges the next capactitor. This works as long as VC_i+VDD is larger than Vdiode+VC_i+1. Because this circuit is current controlled, connecting a voltage source to the nodes 1 and 2 will create a spike current. What I wonder is why one typically uses inductor-based boost convertors[4] for power supplies and not charge pumps. Maybe diode losses? I had this crazy idea of using the bounces of a switch to perform the initial transitions necessary to put a charge on a capacitor enough to bootstrap a microcontroller into driving the pump itself. Apparently the term "charge pump" is used also in PLL[3] circuits, which are used in voltage->frequency converters like [2]. This is where I encountered it today. [1] http://en.wikipedia.org/wiki/Charge_pump [2] http://www.national.com/mpf/LM/LM2917.html [3] http://en.wikipedia.org/wiki/Phase-locked_loop [4] http://en.wikipedia.org/wiki/Boost_converter Entry: booting msx Date: Mon Jun 22 02:02:27 CEST 2009 1. io ports 00-3F are available. this could be used to connect parallel interface to PIC. 2. how to boot? allow for memory mapped access + waitstates? [1] http://www.futurlec.com/Memory/28F010.shtml [2] http://www.futurlec.com/Memory/28F256.shtml [3] http://en.wikipedia.org/wiki/JEDEC_memory_standards Entry: simpleshare board Date: Fri Jul 10 15:55:55 CEST 2009 serial: 2x5 header[1]: pin 1 = logic high (3.3v) pin 2 = CTS pin 3 = Tx pin 4 = DSR pin 5 = RTS pin 6 = CD pin 7 = DTR pin 8 = RI pin 9 = Rx pin 10 = GND [1] http://openmss.org/forum/viewtopic.php?f=9&t=517 Connecting /dev/ttyUSB1,b115200,raw,echo=0 to - CFE version 1.2.14 for BCM94780 (32bit,SP,LE) Build Date: Tue Mar 15 13:14:24 PST 2005 (builder@nlab-sv1-builder) Copyright (C) 2000,2001,2002,2003 Broadcom Corporation. Initializing Arena. Initializing Devices. et0: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 et1: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 CPU type 0x29006: 264MHz Total memory: 0x2000000 bytes (32MB) Total memory used by CFE: 0x80300000 - 0x80442910 (1321232) Initialized Data: 0x8033CD30 - 0x8033F560 (10288) BSS Area: 0x8033F560 - 0x80340910 (5040) Local Heap: 0x80340910 - 0x80440910 (1048576) Stack Area: 0x80440910 - 0x80442910 (8192) Text (code) segment: 0x80300000 - 0x8033CD30 (249136) Boot area (physical): 0x00443000 - 0x00483000 Relocation Factor: I:00000000 - D:00000000 Device eth0: hwaddr 00-01-6C-BD-1E-1A, ipaddr 1.1.1.122, mask 255.255.255.0 gateway not set, nameserver not set Restoring NVRAM...done^Mÿ CFE version 1.2.14 for BCM94780 (32bit,SP,LE) Build Date: Tue Mar 15 13:14:24 PST 2005 (builder@nlab-sv1-builder) Copyright (C) 2000,2001,2002,2003 Broadcom Corporation. Initializing Arena. Initializing Devices. et0: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 et1: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 CPU type 0x29006: 264MHz Total memory: 0x2000000 bytes (32MB) Total memory used by CFE: 0x80300000 - 0x80442910 (1321232) Initialized Data: 0x8033CD30 - 0x8033F560 (10288) BSS Area: 0x8033F560 - 0x80340910 (5040) Local Heap: 0x80340910 - 0x80440910 (1048576) Stack Area: 0x80440910 - 0x80442910 (8192) Text (code) segment: 0x80300000 - 0x8033CD30 (249136) Boot area (physical): 0x00443000 - 0x00483000 Relocation Factor: I:00000000 - D:00000000 Device eth0: hwaddr 00-01-6C-BD-1E-1A, ipaddr 1.1.1.122, mask 255.255.255.0 gateway not set, nameserver not set Waiting to load image on IP 1.1.1.122, ^C to abort...Failed.: Timeout occured Loader:raw Filesys:raw Dev:flash0.os File: Options:(null) Loading: .. 3732 bytes read Entry at 0x80001000 Closing network. Starting program at 0x80001000 Entry: Avnet Xilinx Spartan-3A FPGA board Date: Fri Jul 10 19:45:35 CEST 2009 So.. How to get this going. I copied the DVD to my HDD. It has version 10 of the tools. Ccurrently online it's 11, but quite a download so let's stick to the DVD. It includes software and evaluation versions of: - ISE Foundation - ISE WebPACK - ChipScope - PlanAhead - Platform Studio + EDK - System Generator for DSP and AccelDSP Synth Tool A description here[6]. Let's not bother with evaluation software and stick to things that are going to stay running. I suppose that would be WebPACK The tools need registration[1]. Registration ID: 1A9EAGT1TMJXSWSEXCZNG2360 Hmm.. Apparently the ISE WebPACK 10.1 doesn't run on 64bit, and in sid the ia32 stuff seems broken. Maybe 11.1 works with 64bit? Let's download it overnight. Next: quick start guide[2]. As far as I understand, the board is programmable through the PSoC over USB. I suppose the USB emulates a standard serial port. Are there any linux tools? Yes[3]. The Video[4] talks about SRAM + 16 multipliers on the Spartan-3A. What else does it have? Ok. Me like: apparently the board presents itself as an cdc_acm device. You can just get the interactive console using a terminal emulator. Ok. The linux utility can be found on google code[5]: svn checkout http://avs3a.googlecode.com/svn/trunk/ avs3a I use this wrapper script: [ -z "$1" ] && echo "usage: $0 " && exit 1 exec avs3a -s -p /dev/ttyACM0 -b $1 Now, the tools. I can start ise as Xilinx/11.1/ISE/bin/lin64/ise. It asks me what kind of project I'd like to start and I pick vhdl. Are there any examples to start from? It seems XST is the (command line [7]) synth tool. Next is maybe the ISE tutorial[8][11]. Chapter 2, HDL based design is what I want. Is it possible to bypass the IDE for now and go for straight VHDL -> bitfile? Also, there's a forum about the board[9]. A learning blog about this board[10]. Looks like the Xilinx tools use the Tcl language. [1] http://www.xilinx.com/register [2] https://www.em.avnet.com/common/poptxn/0,2741,RID%253D%2526CID%253D46501%2526CAT%253D0%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html?file=/files/177/s3aeval_quick_start_10_1_01.zip [3] http://www.nt7s.com/blog/2008/09/configuring-the-avnet-spartan-3a-eval-board-on-linux-alpha/ [4] http://www.youtube.com/watch?v=f1Mh8F0kVXE [5] http://avs3a.googlecode.com [6] http://www.xilinx.com/univ/dtools.htm [7] http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0032_6.html [8] http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise11tut.pdf [9] http://community.em.avnet.com/t5/Spartan-3A-Evaluation-Kit/bd-p/Spartan3A [10] http://blog.nirosoftware.com/ [11] http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm Entry: Spartan-3A XC3S400A Date: Sat Jul 11 08:50:51 CEST 2009 Data sheet 3A family[1]. The FPGA is built out of 5 types of blocks: CLB (logic + FF), IOB, Block RAM, Multiplier Blocks, DCM (clock management). [1] http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Entry: I2C on PIC Date: Thu Jul 16 16:35:19 CEST 2009 Does it require external pullup? Is this maybe better to do anyway to make the setup symmetrical? [1] md5://1997353320958cc168dfb19e7e6a1a6d (4525) [2] http://en.wikipedia.org/wiki/I2c [3] http://www.robot-electronics.co.uk/htm/using_the_i2c_bus.htm Entry: FPGA vs. CPLD Date: Sun Sep 27 09:33:32 CEST 2009 Hugh Aguilar mentioned that for (Forth) processor implementation, CPLD might actually be better than FPGA. I'm not sure why though.. The only thing I found is that FPGA is better for applications that need a lot of registers. Entry: MyHDL Date: Fri Oct 2 13:25:36 CEST 2009 MyHDL[1] by Jan Decaluwe[2]. An LtU thread here[3]. An EE times article here[4]. A python-based HDL & modeling tool based on generators and decorators. In MyHDL, classic functions are used to model hardware modules. In particular, the parameter list is used to define the interface. Nested functions, generators and decorators should map cleanly to lambda abstractions, lightweight threads and mixins. I like the fact that generators are used instead of classes. This seems to be quite natural, as most OO-based dataflow code is centered around a 'process' method. Python generators are not generators in the traditional sense (they wrap just an instruction pointer, not a call stack), so a state-machine model is sufficient to implement them. This principle should be mappable to C code in a straight way generation of fast simulators. One of the more interesting aspects of MyHDL is the way in which conversion to Verilog is done[3]: The conversion does not start from source files, but from an instantiated design that has been elaborated by the Python interpreter. The converter uses the Python profiler to track the interpreter's operation and to infer the design structure and name spaces. It then selectively compiles pieces of source code for additional analysis and for conversion. This is done using the Python compiler package. [1] http://www.myhdl.org [2] http://www.jandecaluwe.com/ [3] http://lambda-the-ultimate.org/node/1258 [4] http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=177101584 Entry: VHDL Date: Fri Oct 2 15:03:43 CEST 2009 A tutorial[1]. [1] http://www.gmvhdl.com/VHDL.html Entry: Hints from Expert Date: Fri Mar 12 11:33:39 CET 2010 - use wide concave tip for soldering SMD: fix ends first. - dip wick in liquid flux before using to remove excess flux - use liquid flux with nail polish brush - solder 0805: put drop of solder on 1 end pad, solder one side first holding component with tweezers. - bga: he uses pick & place Entry: MSP430 in PDIP Date: Tue Aug 24 00:48:38 CEST 2010 Available in PDIP for the clumsy perfboard solderer. [1] http://www.embeddedrelated.com/groups/msp430/show/42099.php [2] http://www.ti.com/ww/en/mcu/valueline/index.shtml?DCMP=Value_Line&HQS=Other+BA+430value-promo [3] http://en.wikipedia.org/wiki/MSP430 [4] http://mspgcc.sourceforge.net/ [5] http://hackaday.com/2010/06/22/ti-makes-a-big-bid-for-the-hobby-market/ Entry: Creative use of SPDIF and 10Mbit Ethernet Date: Tue Nov 16 12:04:43 EST 2010 ( Bored with the serious stuff: pointless hacking time. ) I'd like to use the coax SPDIF on the Delta1010 to transform raw binary data to a PIC chip. How to proceed? For max SR of 96kHz we have 2x24 bit channels or 4.608 Mbit/sec. Same for ethernet? Problem there is probably generation of CRC checksums. [1] http://en.wikipedia.org/wiki/AES/EBU [2] http://en.wikipedia.org/wiki/Ethernet_frame Entry: Canon A540 firmware Date: Fri Nov 19 08:02:51 EST 2010 http://chdk.wikia.com/wiki/CHDK Canon PowerShot A540 P-ID:311B NT Firmware Ver GM1.00B E18 Jan 31 2006 11:02:45 Entry: Room acoustics Date: Sun Nov 21 11:21:08 EST 2010 I've got a 132 Hz resonance in the studio room. From the location of the zero (3/4 between the 2 corners) I think this is mode 2, with the root mode at 66 Hz. Indeed, at 66Hz there's a zero in the middle of the room. The corner-to-corner distance is about 4.5 - 5 meters. At 300m/sec this gives: (/ 300 5) -> 60Hz The distance is then probably more like 4.5 meters: (/ 300 4.5) -> 66Hz Edit: some more measurements. 132Hz is a 2.2 meter wavelength, which is 1/2 the distance between the cross corners. Maybe put a bass trap in one of the corners. [1] http://www.gearslutz.com/board/bass-traps-acoustic-panels-foam-etc/347485-130-hz-peak.html Entry: RC segments Date: Tue Nov 23 18:11:29 EST 2010 Type: tex {\tiny Part of an attempt to revive analog circuit intuition. } Observe the low--pass filter in [1] right before the input of the delay line. It contains 3 sections with a time constant of $22$us, $45$kHz when they would be in isolation. However, they are coupled with the next stages loading the previous. This is why the restor/capacitor ratio shifts: each stage $R/C$ goes times $10$ with $RC=\tau$ constant. Assume the 3 sections are isolated (i.e. there is a unit gain buffer between the RC sections), and assume their time constants are the same. At $f = 1/\tau$, the $3$dB point, the magnitude of the impedance of each capacitor is equal to that of its resistor, though with a $-j = e^{-\pi/2}$ phase shift. The first section's capacitor is then at $-10j$kOhm, while the second is at $-33j$kOhm and the third is at $-100j$kOhm. The point is now that with the buffers removed, and each section loading the previous, the time constants won't shift that much because the loading impedance is quite a bit larger than the capacitor impedance. I.e. $10$ kOhm vs. $33-j33$ kOhm Calculating the transfer function by hand is a bit tedious. Might be best to writ a small program to see how the poles split in terms of the $R/C$ ratio increment per stage. Another approach is to write a form for the infinite chain, and tap it at some point: $$Z_n = \alpha^n R + ( j\omega C a^{-n} + Z_{n+1} ) ^{-1}$$ % [1] http://www.uni-bonn.de/~uzs159/pt2399.html Entry: Printing from OSX 10.5 to cups on linux Date: Sat Nov 27 13:00:41 EST 2010 Pff.. Why do they have to keep changing everything all the time? I used to be able to just add a queue using the CUPS web interface but now it's hidden behind menues, and I get faulty output. Maybe use LPD instead of IPP? Entry: Bass guitar noise pickup Date: Tue Nov 30 19:20:07 EST 2010 I notice a big difference between plugging the bass straight into the Behringer UB1202 or first into one of the pedals: Behringer OD300 or Danelectro FAB Echo. The difference is probably that the UB1202 has a 10k input impedance, and the pedals use a much higher value. Measuring the resistance using a multimeter gives either open circuit or negative resistance. Why is that? Maybe base current from bipolar input stage. It seems that the XLR inputs are 2k6 balanced, while the TRS inputs are 20k balanced. What's the output impedance of the bass? It measures 10k (guitar measures 5k). Then I wonder why all guitar effect schematics I find online have such high input impedances. This seems to significantly increase hum pickup. Going further I found this[1] discussion about pickup impedance. So, the whole story goes like this: a linear transducer can be modeled as a voltage source with series resistor (Thevenin equivalent) or a current source with parallel resistance (Norton equivalent). The question is how to load it. There are 3 extremal points in the load impedance: - high: z_in >> z_out, i.e z_in = infinity: max voltage - low: z_in << z_out, i.e. z_in = zero: max current - matched: z_in == z_out: max energy So I wonder: what about loading with z_in = 0 and measuring current only? [1] http://www.diyaudio.com/forums/musical-instruments/33294-low-impedance-pickups.html Entry: Guitar pickups cont.. Date: Thu Dec 2 00:07:49 EST 2010 What I read online is that a typical pickup has an inductance of 4H. This hits 10k at f = 400 Hz. So the loading should significantly alter the sound. See also measurements here[1]. What I didn't know is that the cable makes such a difference, as the cable capacitance is significant in the RLC chain and can shift the reso freq. [1] http://buildyourguitar.com/resources/lemme/ [1] http://www.geofex.com/effxfaq/distn101.htm Entry: Audio card scope Date: Fri Dec 10 16:12:00 EST 2010 I tried both xoscope and qoscc. First one only uses /dev/dsp which doesn't work for me (unless I have emu jack->dsp) and the second one is way too slow and also seems to be quite buggy. So, let's dig up pdp_scope~ again. At least that will give some control. What I need is: - Triggering - Autoscaling (time and amplitude) - Grids - A pretty display (bresenham / virtual phosphor) Triggering can be best added to creb, as it seems universally useful, also for dynwav. Maybe there is already something like it? Alternatively: use delay lines. They are already part of pd and have exactly what is needed: a variable window into the past. EDIT: wrote a new one[1]. [1] http://zwizwa.be/darcs/scope Entry: Scopes Date: Fri Dec 10 19:10:39 EST 2010 I found the one I have in Belgium on ebay[1]. G72515 Goldstar OS-9020A 2-Ch Oscilloscope 20MHz Finally bought this one[2]. Leader LBO-526 60MHz 2-Channel Dual-Trace Oscilloscope [1] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=330506857430 [2] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=380297166598 Entry: DI box Date: Sun Dec 12 00:51:34 EST 2010 What I need: - 2 inputs - mix (crossfade) knob, or 2 gain knobs. - multi out (+ possibly send level) Entry: Induction motor generator Date: Wed Dec 15 23:02:03 EST 2010 The key to bootstrapping is the residual magnetism in the rotor. Questions: - Where to get low-power, low-rpm motors? - For illustration purpose: how to build 3-phase induction motor from scratch? - Is there a relation between AC freq, RPM and bulkyness? To summarize: 1hp is 750W. [3] claims peak power of 300W. So a 1/2 to 1 hp motor should be enough. [1] http://www.youtube.com/watch?v=ADRK_NkQ-eU [2] http://www.qsl.net/ns8o/Induction_Generator.html [3] http://www.econvergence.net/electro.htm [4] http://www.pedalpowergenerator.com/#FREE Entry: LED lamp controller Date: Thu Dec 16 00:44:50 EST 2010 Got a cheap LED lamp[2]. However, this doesn't seem to work too well from 1.2V rechargables as the voltage drops fast. The LEDs are at 3.5V and the regulator is a 1Ohm resistor. A nice excuse to build a circuit. For a buck-boost converter[1] the LED can be used directly as the switching diode. The only problem is how to measure the current. I don't have low-ohm resistors in stock. It might also be possible to let the LED go out such that voltage feedback can be used. If switched fast enough we won't notice. Depending on the known value of the inductor we can use pulse width timing to charge it up to a certain max current, then let it discharge fully in the LED. When the current goes to zero, the voltage suddenly drops which can initiate a new charge cycle. Problem with buck-boost in [1] is the negative voltage. I.e. using a simple PNP switch, the emittor will be pulled down by the inductor whenever the current is switched off, so the base needs to be tied to the emittor through a resistor. Then switching the base from Vcc/High-Z should work. Problem is that the High-Z voltage on the PIC pin will be the negative inductor voltage, so the protection diode kicks in turning the transistor on again.. Not so simple! Solution might be to add an extra diode, though then the problem is to make it conduct in the first place. Need to read more.. Found this[4]. A different topology though. Starting from such a topology and doodling a bit it seems it's quite simple if the LED can go out during the inductor charge cycle. I arrived at two conclusions: - The buck-boost in [1] needs a PNP transistor switch. (duh!) That way the coil end is at a the collector, and it can go negative without any problems. - Starting from that PNP schematic, it can be inverted by changing battery polarity and using a NPN switch. For 2.2 mH (what I ordered) and a 5V supply it will take 130us to charge the inductor to 300mA. Discharging it through 3.6V will take about 180us. It seems that this really doesn't need a closed loop controller as long as the inductor is fully discharged during the transistor off time. Measuring the voltage across the LED is going to cost two resistors. Then it seems simpler to just use one low-ohm resistor on the transistor emitter to measure the inductor current directly. [1] http://en.wikipedia.org/wiki/Buck%E2%80%93boost_converter [2] http://www.amazon.com/gp/product/B001F1UFR6 [3] http://www.edn-europe.com/buckboostconverterschangewiththetimes+article+2201+Europe.html [4] http://www.digchip.com/application-notes/3/12977.php Entry: Tayda: staple transistor 2n3904 / 2n3906 Date: Thu Dec 16 20:13:25 EST 2010 Cheaper transistor at Tayda: 2n3904 NPN $1.9 http://www.fairchildsemi.com/ds/2N/2N3904.pdf 2n3906 PNP $2.9 http://www.fairchildsemi.com/ds/2N/2N3906.pdf The BC559 / BC549 from Futurlec are $0.08 each. Entry: Using CMOS inverters as linear amplifiers Date: Fri Dec 17 00:11:32 EST 2010 With proper biasing, the s-curve inverter amplitude transfer function can be exploited for smooth distortion. I was thinking about moving this one step further and implement SVFs. TAOE's section on the CMOS inverter mentions the use of CMOS inverters as cheap open loop amplifiers when the waveforms aren't important. It mentions a biasing network with a shunting capacitor that's open loop for AC. This also appears in [3] ("treble boost"). The app note[2] mentions linear (feedback) applications. Questions: - How much current does a 1/2 biased inverter draw? - Can we feed the inverter with a current source to control gain? How are g_m, gain, current and voltage->current related? One strange thing about [2] is that DC gain _drops_ when voltage rises. - How to bias a-symmetrically? Bottom line: * A CMOS invertor behaves mostly like a low-gain opamp with non-inverting input tied to +- 1/2 Vcc. * For distortion, we're interested in the open-loop gain. [1] md5://4547016f823d5ad574cf77c44608409d [2] http://www.qsl.net/l/lu7did//docs/QRPp/TTL_CMOS%20As%20Linear%20Amplifier_AN-88.pdf [3] http://www.aronnelson.com/gallery/main.php/v/WGTP/Red+Rooster.GIF.html?g2_imageViewsIndex=1 Entry: Resistor color code mnemonic Date: Sun Dec 19 21:28:49 EST 2010 Bad beer rots our young guts but vodka goes well – get some now The colors are sorted in the order of the visible light spectrum: red (2), orange (3), yellow (4), green (5), blue (6), violet (7). Black (0) has no energy, brown (1) has a little more, white (9) has everything and grey (8) is like white, but less intense.[8] [1] http://en.wikipedia.org/wiki/Electronic_color_code#Mnemonics Entry: Capacitors and resistors: getting a feel for component values Date: Wed Dec 22 17:01:23 EST 2010 Managing Impedance ------------------ One of the essential elements of good circuit design is to manage the orders of magnitude -- to optimize circuit impedance. Most designs allow to be run at higher current/voltage which is good for noise immunity but bad for component cost (bigger size) and operating cost (larger power cost, heat production). I remember this to be one of the earliest discouraging problems I ran into, trying to obtain expensive large Polypropylene capacitors for a filter circuit I designed on paper because the resistors values I used where on the small side. In those days I had nobody to turn to and no access to information that was in a form I could digest, so I gave up. In recent years and especially the last couple of weeks getting my hands dirty and reading schematics, these things have become more clear to me. So, as an illustration, here's a problem I ran into which hints at the "muscle memory" you need to create about resistor and capacitor values. Dynamic range ------------- The problem is that both resistors and caps have a large dynamic range of useful values -- about 8 decades each. - 0.1 (10^-1) -> 10M (10^7): - 1000u (10^-3) -> 10p (10^-11) As a result the time constants that come from combining these have about 15 decades. That's a pretty large time scale from 11 days to 1 picosecond (1 teraHz). The time scales for audio processing are luckily a bit less large, about 3 decades from 20Hz to 20kHz, or 4 from 5-50kHz depending on how you count. However, due to the large range of R and C, there are about 10 - 11 decades of impedance to choose from when RC time constants are given. That's quite a lot. Most of this is ruled out as either too high (instrumentation amplifier) or too low (power amp), which leaves a good 3-4 decades where resistors range from 220Ohm to 2M. The Art of Electronics[1] (p. 279) has a rule of thumb that that says to pick a capacitor value in based of 10uF / Hz. This places resistor values around 10-20k. It doesn't really explain why. At another point ([1] p. 275) it mentions to pick resistor values in the 10k-100k range, as lower values tend to get closer to the open loop impedance of opamps as frequencies rise. My guess is that higher resitor values are to be avoided because of noise. (TODO: add some quantitative explanation here). The problem ----------- Currently I have only 50k dual log (A-type) potentiometers I want to use in a SVF filter. The lowest frequency of interest is 20Hz, which brings the capacitor value to about 160nF, which rounds down (frequency) to 220nF. That seems rather large for a ceramic cap. The largest I have here is 100nF, and it's a ceramic multilayer (the microphonic ones). The smallest ceramic disc cap I have is 47nF (473). Let's check some Futurlec[2] prices to see where they start to rise significantly. Capacitance Max Smaller Price Largest Type ----------------------------------------------------------------------- 100nF 2200nF $0.07 $0.12 $0.60 100V Mylar 150nF 2200nF $0.06 $0.15 $0.30 50V Multilayer Ceramic 100nF 100nF $0.05 $0.10 $0.10 50V Ceramic Disc That looks like a trend. From the cost perspective it seems to be a good idea to keep capacitors below 100nF, which means impedances should be 100k or above for to get to RC frequencies below 20Hz. Conclusions ----------- For full audio range SVF time constant setting, use a 220n cap if 50k is given, but if possible, raise the POT to 500k and use a 22n cap. EDIT: For SVF, the loop gain can be lowered to end up with smaller cap values for the same frequency range. [1] isbn://0521370957 [2] http://www.futurlec.com/Capacitors.shtml Entry: CPLD Date: Sat Dec 25 12:23:37 EST 2010 The Atmel ATF20V8B[1] seems like an interesting part to play with. I found it looking for PDIP CPLD. [1] http://www.atmel.com/dyn/products/product_card.asp?part_id=2084 Entry: Weird brain fart: open vs. closed loop bode plots Date: Sun Dec 26 11:56:12 EST 2010 Context: state variable filter. If 2 integrators produce 180 degree phase shift, why does the circuit oscillate where loop gain = 1, and not where gain is larger? Very bad formulation and I don't know if I can fix that, but the idea is this: don't confuse time domain behaviour with s-parameter model. If the frequency is well below 1/tau the integrators are "fast enough" and will follow the input signal. Entry: Pedal power Date: Tue Dec 28 22:11:25 EST 2010 1. Brushless. Without a doubt. Both for aging and efficiency. 2. Induction motor + some way to bootstrap it in case it is not magnetized, i.e. smaller synchronous motor. 3. Battery / supercaps. Some form of storage is necessary. Lead-acid doesn't work indoors. Can it be made with minimal storage? I.e. keep the energy mostly in "human" form, but allow for catching breath and changing operators. Entry: Generator from 1-phase motor Date: Wed Dec 29 22:48:42 EST 2010 MOTOR A 1-phase induction motor motor is actually a 2-phase motor, with a capacitor providing the +- 90 degree phase shift. Is it possible to ditch the cap and use it in proper 2-phase? I.e. is the 2nd phase somehow cripled for power rating? Context: low-power 3-phase motors are expensive. Low power 1-phase are almost free (old junk). It migt be more interesting to concentrate on recycling junk to build crank generators. However, a 3-phase is supposed to be more efficient[1]. Why is that? Is it true that a 1-phase motor does not give constant power? This makes sense, as both V and I go through zero at the same time (ignoring coil inductance). ELECTRONICS For low rating (+- 100 W) the electronics are also going to be a lot cheaper. Where to get transistors? [1] http://users.telenet.be/b0y/ Entry: Staapl nudge app: LED driver Date: Thu Dec 30 16:01:30 EST 2010 What should be the app driver for cleaning Staapl up to a usable s-expression level? What about an LED boost converter? Entry: BEAM robotics Date: Fri Jan 14 22:54:17 EST 2011 KISS analog control. [1] http://en.wikipedia.org/wiki/BEAM_robotics Entry: Breadboarding Date: Sun Jan 16 19:04:22 EST 2011 I've been looking into some straightforward way to make prototypes. What I want to do is very simple: analog circuits with a lot of discrete components. However, I feel I loose too much time on building and debugging bad solder joints. Options: * I've been using pad-per-hole perfboard for a while. I like it better than stripboard because it's possible to design a fairly compact 1-sided PCB with fat tracks and copy it using component leads. * Home-made etched PCBs. It seems that most options are quite a lot of work. Toner transfer, etching, drilling. * Home made milled PCBs. Requires some equipement. * Fabbed PCBs. Either expensive, or long lead time. * Wire wrap. I'm gathering some tools to try it out, but it seems expensive too. * Combination soldering / wire wrap. Might be best for what I want to do, but need to try first. One thing I ran into though is the over/under rule for wire wrapping. See[1] : Put in all your level 1 to level 1 wires first, then the level 2 to level 2. The only level 2 to level 1 wire should be at the end of a chain. If you follow this rule, you never have to take off more than 3 wires to make a change. I wonder if this approach makes sense for pad-per-hole breadboarding too: don't worry about component placement or bending wires, just construct all nets as chains with max 2 connections per component pin. [1] http://www.fliptronics.com/tip0003.html Entry: 1/f noise Date: Mon Jan 17 11:28:59 EST 2011 I read recently that the 1/f noise in amplifiers is essentially not bounded from below in frequency, meaning it can become very problematic for true (non-leaky) integrators. I don't know the exact context of this, but that seems like a strange phenomenon. What is this about? [1] http://en.wikipedia.org/wiki/Flicker_noise Entry: Translinear Principle Date: Tue Jan 18 23:25:09 EST 2011 I can't remember running into the Translinear Principle (TLP) before[1], especially not in school. ( Of course I did run into log/antilog converters and current mirrors. ) The TLP is a product rule for currents through translinear elements (TE). To simplify, a TE is a forward biased PN junction, i.e. a diode or BJT BE junction. It's quite nifty: * Construct a loop that goes through TEs traversing each element forward or backward. A loop needs to contain an equal amount of TEs traversed in the 2 opposite directions: clockwise (CW) and counter clockwise (CCW). * By Kirchoff's law, the sum of all the forward voltages of CC TEs equals the sum of all the forward voltages of the CCW TEs. * By the exponential V->I law, this implies that the product of the forward currents through all the CC TEs equals the product of all the forward currents through all the CCW TEs. [1] http://en.wikipedia.org/wiki/Translinear_circuit Entry: Opening up FV6020 Date: Thu Feb 3 19:24:14 EST 2011 Let's look inside. SOC: Infineon PSB 21553 E V1.4 INCA-IP-S RAM: SAMSUNG 434 K4S641632H-TC75 FLASH: 29LV160 TP7 on the board has the serial console. It's the first time I followed a point and shoot approach. 1. Identify ground to connect to scope probe ground. 2. While booting, identify which pins are high: they are either idle serial, or VCC. 3. The TX line will clearly show signal. The other one is VCC. 4. Identifiy ground by measuring resistance to the known ground connector. 5. Look on the board: 2 traces run to the SOC, this is RX and TX, so that identifies RX and confirms TX. TP7 TX . . RX . . 3V . . GND Baud rate is 115200: Attaching interface lo0...done error column the TSF reg is 0x2 Starting at 0x80010000... VLAN_CTRL: PC LAN CPU send only to Members: + - - accept untagged packets: + + + VLAN aware: NO VLAN_CTRL: PC LAN CPU send only to Members: + + - accept untagged packets: + + + VLAN aware: NO VLAN_CTRL: PC LAN CPU send only to Members: + + + accept untagged packets: + + - VLAN aware: NO Port VLAN ID PRIO PC : 0x0001 ( 1) 0 Port VLAN ID PRIO LAN : 0x0002 ( 2) 0 VLAN table entry added: index = 0, VLAN ID = 1 (1), Ctrl = 65 VLAN table entry added: index = 1, VLAN ID = 2 (2), Ctrl = 66 VLAN_CTRL: PC LAN CPU send only to Members: + + + accept untagged packets: + + - VLAN aware: YES ----->equal++sw0x 807ffe00 (8041e760tRootT ask------>inaterface name ): swVSW END LOAD unit 0x0807f fe00 (tRootTask): VSW END LOAD Attached TCP/IP interface to sw unit 0 Attaching interface lo0...done Adding 9123 symbols for standalone. VxWorks Copyright 1984-2002 Wind River Systems, Inc. CPU: INCA-IP BSP Runtime Name: VxWorks Runtime Version: 5.5.1 BSP version: 21553.1.0.1 1.14.0.3 Created: Jan 17 2007, 10:27:33 WDB Comm Type: WDB_COMM_NETWORK WDB: Ready. -> Read configuration from flash ..............................Finished Initializing the DSP module 0x806f4950 (tGwStart): msqDTMF is generated,code is 0x806de9b0 Download successful! 0x806f4950 (tGwStart): msqDTMF is delete,code is 0x0 0x806f4950 (tGwStart): msqDTMF is generated,code is 0x806de9b0 ..............................Finished Start up network module ..............................Finished Start up SIP module ..............................Finished Start up IAX2 module ..............................Finished Start up call manager module ..............................Finished Start up config mangement system..............................Finished uiCallInform:0,0 started, version 2.0rc1 cachesize 150 Login: [MGR] | NOTICE |DHCP client start OK [MGR] | INFO |DHCP Server Start Success [MGR] | NOTICE |NAT module Start Successfully [SIP] | WARNING|info: Starting osip stack and osipua layer. [SIP] | ERROR |info: port already listened [SIP] | NOTICE |allocating transaction ressource 1 841012261-270525659 [SIP] | NOTICE |allocating NICT context [SIP] | WARNING|info: Entering osipua thread. [MGR] | INFO |>chan 0 is handed up,status:0 uiCallInform:3,0 Entry: Interfacing 3V3 and 5V applications. Date: Fri Feb 4 13:16:18 EST 2011 From [2]: "There are many ICs available on the market that are specifically designed to translate between logic levels. We've never used any of them!" The basic ideas are: * 5V -> 3V: use a current limiting resistor. This requires the 3V3 input to be protected with clamping diode the 3V power supply! * 3V -> 5V: no resistor necessary, inputs are compatible. I guess it doesn't hurt to place one anyway in case master/slave roles are reversed? SPI bus with the 5V device as master, as seen in the example in [2]: * MISO: master input slave output (3V) * MOSI: master output slave input (5V) * SCK: master clock (5V) [1] http://www.nxp.com/documents/application_note/AN240.pdf [2] http://www.sparkfun.com/tutorials/65 Entry: 3.3V from different regulator Date: Sat Feb 5 09:50:00 EST 2011 I have a bunch of regulators, but no 3.3V ones. If I recall there is a trick to get a different voltage from a linear regulator by changing the feedback path.. How did that go? See data sheet [1]. That only shows how to raise the voltage though. This seems to be the default configuration for a component like [2] which has a 1.25V reference. The ARM board uses the L4931C33[3]. What about using a red LED to take the voltage drop/ That should be about 1.8V? ( Measured: the bright reds I have here are 1.67V which is pretty close to perfect. ) So from 5V we go through the led to a buffer cap. Placing a resistor parallel to the buffer cap should prevent the LED to turn off, which would lower its voltage, ultimately charging the cap to 5V if there is no load attached. Hmm.. There's another problem: 5V across the LED when cap is not charged, so this would need a current limiting resistor also. But if the input also has a cap, that problem is solved. Seems quite a hack.. Ha, I found somebody suggesting it here[4]. Anyways. I placed an order at Tayda. Maybe visit RadioShack for some 3V3 regulators. Other than that, I do have all components to solve my most basic need. [1] http://www.futurlec.com/Linear/78L05.shtml [2] http://www.national.com/mpf/LM/LM317.html#Overview [3] http://www.st.com/internet/analog/product/63164.jsp [4] http://www.electro-tech-online.com/general-electronics-chat/88621-convert-5v-dc-3-3v-dc.html [5] http://www.4uconnector.com/online/itemagrid.asp?seriesdesp=2.54+FEMALE+HEADER+PLUS+TWO+BASE+DIP+STRAIGHT+HEIGHT%3D13.59MM&seriesno=0197&GroupNo=01&groupdesp=Pin+%2F+Female+Header&itemnum=5324&sample=&seriesnum=96& Entry: SPI basics Date: Sat Feb 5 12:16:23 EST 2011 The SPI bus is a point-to-point connection with one master and one slave. The master generates the clock. There are 4 signal lines: MISO: master input slave output MOSI: master output slave input SCK: master clock SS: slave select (CS: chip select) The MISO/MOSI naming connects pins with same names. An alternative naming scheme: SDO: serial data out SDI: serial data in names pins according to data direction. This requires SDO<->SDI connections. Some remarks: * Implicit in what I read, but it seems that master/slave choices are a property of the circuit design, i.e. they won't change during operation. As a consequence, all signals are uni-directional. It also seems plausible that a "dumb" device like a sensor or storage device will not be master. * When a slave is not enabled (SS high) the MISO (a.k.a. SDO) pin is in high-Z configuration. Does this require a pullup/down on the bus to avoid noise? I guess not as the input can be ignored by the master during the time no slave is active. * Communication is full duplex when the master drives the clock. There are 4 clock modes: 2 clock polarities times 2 read/write edge configurations. * Data seems to be MSB first (from SST25 and PIC18 data sheet). However SPI transfers bits, not bytes or words so it seems to be up to the device. * PIC18F2620 can use TMR2 / 2 or FOSC / 4,16,64 as master clock freq. ( While the other times have 2^n subdivisions, TMR2 has a period register so can be quite flexible. ) * In both the PIC18 and AT91SAM7 data sheets the master mode sends 8 bits at a time, sending MSB first. ( The PIC18 has one dead cycle after the 8th bit is sent out with the last asserted data bit still present. I've seen this using the SPI out as a video shift register. Since this is also a dead clock cycle, it doesn't matter for slaves. ) [1] http://en.wikipedia.org/wiki/SPI_bus Entry: Synth bus Date: Sat Feb 5 12:51:23 EST 2011 Insead of I2C it seems better to use a daisy-chained SPI bus, as it is easier to transport fixed sample rate PCM signals using circuit-switching. Entry: New PIC18 chip : PIC18F14K22 Date: Sat Feb 5 16:39:02 EST 2011 PIC18LF14K22-I/P * 20 pins, PDIP available * nanowatt XLP * internal oscillator up to 64MHz (16MIPS) * 64MHz (16MIPS) at 3V * 1.8 - 5.5V * SPI/I2C http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en538160 PIC18LF46K22-I/P, as above except: * 40 pins, PDIP available * 2x SPI/I2C 2xUART * 28 ADC channels http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en547757 That one caught my eye, but there are many more. Might need to do a sheepsint update ;) EDIT: looks like these new chips are not supported by PK2. They are still supported in the ICD2 though. But then the PK2 product page says it can debug the PIC18F46K20. Entry: Prototyping fear Date: Sat Feb 5 22:08:19 EST 2011 Next thing to do is to get over my prototyping fear. Basic problem is that I'm still very error prone and not so systematic building prototypes. I loose a lot of time fretting over things because change is expensive too. This is a problem and needs to be solved. Entry: Bitbang SPI on FT232RL Date: Fri Feb 11 07:00:34 EST 2011 Since I have several of these FTDI USB TTL cables it might be interesting to standardize on a connector for SPI. Is there anything that already does this? See [1][2]. So for SPI, the mapping that makes most sense is: TXD MOSI RXD MISO RTS SCK CTS CS with possibly SCK and CS swapped. [1] http://www.ftdichip.com/Support/Documents/AppNotes.htm [2] http://hackaday.com/2009/09/22/introduction-to-ftdi-bitbang-mode/ Entry: Fix electronics prototyping Date: Sun Feb 13 20:54:06 EST 2011 I was watching [1]. It was a bit disappointing after all the big words in the abstract. And as he explained in the talk: it doesn't solve vias. However, his problem exposition in the beginning is spot on though: electronics prototyping sucks. What is needed is something thoroughly different. I don't think it's possible to improve on PCBs for mass production, but for prototyping they suck. Fixing the prototyping problem would mean a revolution. What struck me in the talk is that you really just need to solve the 3D printing problem, where your "bricks" are 2 kinds: conducting and non-conducting. In this case you don't even need layers, just a possibility to cross wires, i.e.: . . . . . . X X X . . . . . X o X . . . . . here "X" is the insulator, and "." and "o" are the conducting wires. So instead of printing with voxels (volume pixels), why not print with wire strips? If there is no etching, there is no need for rounded corners, and a grid can be used. * Pick-and-place machine that places small pieces of wire on some kind of (embossed?) substrate, and then point-solders them where they need to be joined. * Cutting trenches, filling with molten metal? * Start with a patterned pcb and cut traces? [1] http://events.ccc.de/congress/2010/Fahrplan/events/4099.en.html Entry: Building GDB for arm-eabi Date: Tue Feb 15 15:47:07 EST 2011 # It's actually quite straightforward: wget http://ftp.gnu.org/gnu/gdb/gdb-7.2.tar.bz2 tar xf gdb-7.2.tar.bz2 mkdir -p gdb-7.2/build/arm-eabi cd gdb-7.2/build/arm-eabi ../../configure --target=arm-eabi make sudo cp gdb/gdb /usr/local/bin/arm-eabi-gdb-7.2 EDIT: make sure XML support is enabled (will do by default if libexpat-dev is installed) otherwise the openocd -> gdb memory map transfer won't work which breaks many things. EDIT: to enable python extension (apt-get install python-dev) ../../configure --target=arm-eabi --with-python Entry: Microchip idVendor sublicense Date: Thu Feb 17 11:08:53 EST 2011 It's possible to ask Microchip for a free product ID under their vendor ID 0x04D8 for product quantities under 10000. They reserve the right to revoke at any time. [1] http://ww1.microchip.com/downloads/en/AppNotes/Application%20for%20USB%20Vendor%20ID%20Sublicense.pdf Entry: Soldering SOIC Date: Sat Feb 26 23:04:19 EST 2011 Valt reuze mee! It's not such a big deal. Up to now my shaky hands have only attempted DIP soldering. However, for a contract job I was not able to find DIP components for prototyping, so I had to get over my SMD fear. 1. Dead-bug + AWG30 kynar wire wriap wire. Because I had no boards at all, this is what I tried first. The soldering by itself wasn't so hard: just make sure there is a bit of solder on the iron and touch the wire and pin. Getting the wire and pin to sit still is another matter. A 2-arm helping hand is what works well here. 2. SOIC -> DIP adapter. I followed the advice from many tutorials online: put a good amount of flux on the pads (I use a nail polish bottle & brush) and place the component on the pads. The flux will make it stick a bit, but you can still move it around. Solder one pin on one corner. I had to press the chip down to make sure it didn't slide, as my shaky fingers would push it out of place when I hit the side. If it doesn't move any more, solder the opposite corner. Be very careful not to bump the chip causing misalignment. Once two corners are fixed, just add some flux on the pins, put some solder on the tip (I'm using a slanted flat tip) and heat the pins one by one, boiling the flux. I don't think I'll be using the dead-bug style again. While straightforward, it is a lot of work stripping & aligning wires, and the result is fragile. Small adaptor boards are cheap on ebay. Entry: ARM in SOIC Date: Sat Feb 26 23:21:19 EST 2011 Luminary micro[1]. [1] http://www.luminarymicro.com/products/lm3s101.html Entry: SPI SRAM Date: Sun Feb 27 14:29:02 EST 2011 The Microchip 23A256 256kbit SPI SRAM[1] arrived. I wonder if I can use this to implement a TV/VGA frame buffer. Does it support continuous bit stream to dump out serial bits without any gaps? If so, readout can be used to draw scan lines, and the dead time can be used to upload data. In the datasheet[2] it is mentions that it supports sequential operation, so giving it a proper clock will just dump out all the bits. The remaining problem is then to detach the RAM SPI data output from the frame buffer output when we're updating. This can be done using a simple resistor connected to a PIC pin that's kept floating when the RAM is supposed to drive the output, and tied high or low when it is not. Other applications are 1 bit sample playback. [1] http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en539040 [2] http://ww1.microchip.com/downloads/en/DeviceDoc/22100E.pdf Entry: Binary modulation Date: Sun Feb 27 14:43:45 EST 2011 What about this: use a pre-computed modulation pattern stored in a SPI Flash, off-line optimized for a certain circuit. Even on-board flash and the synchronous output port could work fine.. Entry: Analog audio in Date: Sun Feb 27 19:14:08 EST 2011 The trouble with DIY measurement gear is always the front end, and getting the data in the computer. For the PIC18 my current option is only 12Mbit USB (full-speed). Ethernet is possible, but only at 10Mbit. So the PIC doesn't seem to be a good solution for anything more than audio rate. I've rencently been using AT91 for a project. I have a AT91SAM7X-EK board with 100Mbit ethernet. The USB only goes up to 12Mbit also. So two questions: * What is the fastest rate the AT91 can send? * What is the max sample frequency of the ADC? 1.25 uS conversion time 384 ksps The ADC speed isn't so high. Max data rate (10 bits) is just below 4Mbit. There should be no reason that doesn't work.. Entry: Upgrading OLS firmware Date: Sun Feb 27 23:20:40 EST 2011 $ svn checkout --username anonymous http://gadgetforge.gadgetfactory.net/svn/butterflylogic//trunk/package/OLS_Upgrader $ cat vars.sh export PATH=`pwd`/linbin64:$PATH $ sh ols-upgrader.sh I'm not sure if it worked correctly, but at least I don't get garbage any more when enabling RLE. The upgrade gave the following message, but I guess that's the old FW. ... Logic Sniffer ROM loader v0.3 (November 9, 2010) Opening serial port '/dev/ttyACM0' @ 921600 ... OK Found OLS HW: 1, FW: 2.3, Boot: 2 Found flash: WINBOND W25X40 OLS switched to bootloader mode ... Entry: OLS clocked input Date: Tue Mar 1 23:30:05 EST 2011 It would be very useful to be able to gather data with one of the pins acting as a clock input. [1] http://www.delicious.com/doelie/openbench Entry: DC amp Date: Thu Mar 10 20:27:10 EST 2011 For 9V battery-powered circuits it might be simplest to use a buffered 100k/100k voltage divider as the GND connection for inputs and outputs. It might introduce offset for high gain apps, but it does away with capacitors and biasing issues. Trouble is that you can't use the TRS jack trick to power on the circuit. Entry: Phantom power Date: Tue Mar 15 20:29:01 EDT 2011 I need a DI box and I'd like to feed it from the mixer's phantom power as I don't want to mess around with batteries that go dead or power supplies that can introduce more ground loops. Something like this[1]. Hmm.. Shopping around I find a cheap transformer-based passive one[3]. EDIT: actually, it's only a couple of milliamps. Closed circuit 14mA if the spec is followed. [1] http://www.amazon.com/Rolls-ADB2-Phantom-Direct-Box/dp/B00102VVZA [2] http://en.wikipedia.org/wiki/Phantom_power [3] http://pro-audio.musiciansfriend.com/product/Live-Wire-Solutions-SPDI-Passive-Direct-Box-with-Attenuation-Pad?sku=150449 Entry: Mixer feedback Date: Thu Mar 17 09:45:40 EDT 2011 I had some fun yesterday with the new Behringer Xenyx 802 mixer, some patch cords and a distortion pedal. The mixer has only one effects send which I used to feed the distortion pedal. See description[1] and recording[2]. This makes me think that an interesting application would be to build a circuit that has this kind of patching hard-coded, and just play with the feedback gains. To some extent it might be possible to automate the "chaos search". What I do manually is to turn some knobs and look for transition points. Then I apply minuscule changes to find the chaotic regions inbetween. [1] http://mala.wha.la/pool/moderately-extraterrestrial.txt [2] http://mala.wha.la/pool/moderately-extraterrestrial.ogg Entry: Unofficial PIC18 BDM debug module desciption Date: Sun Mar 20 22:54:22 EDT 2011 Jaromir Sukuba has published some info on the PIC18 in-circuit debugger functionality[1]. Great! [1] http://jaromir.xf.cz/hdeb/bdm/bdm.html Here's a mirror: ----------------------------------------------------------------- This page contains material which is derived partly from public domain information, but mostly guessed only. It seems to work, however. Use this information at your own risk, for personal research and personal use only. Author is not responsible for any damage, like broken PICs, crashed computers, sleepless nights, unsatisfied wives etc... No commercial use allowed. Microchip encorporates background debug module (BDM) module in all PIC18F devices, enabling them to be debugged in circuit. First device having BDM on board was PIC16F877 and derivatives - and this is the last device with offcial BDM module description. Following devices kept this secret, also all members of newer PIC families were released without description how their debug module works. I'll try to do this for PIC18 devcies in this document. Entering debug mode ------------------- For using debug mode, two conditions had to be satisfied: * disabling all code protect bits in configuration bytes * programming DEBUG configuration bit into logical 0 (this forces RB6 and RB7 to debug IO pins) There is reset (POR, MLCR or by executing RESET instruction) after programming, before entering debug mode. Actual entering debug mode is done in one of four ways: 1. by introducing 1->0 transition on RB6 pin 2. on POR/MCLR reset 3. on breakpoint 4. or after executing any instruction while single stepping is active First two conditions can be achieved without prior entering debug mode, another two (setting breakpoint or enabling single stepping) are possible only during debug mode. Entering BDM means entering vector at address 0x200028. There must be instruction to jump at address in valid FLASH range, where debug executive resides. Leaving debug mode ------------------ Once debug mode entered, it can be left by executing undocumented TRET instruction. This instruction seems to be identical to RETURN instruction, but it also clears DEBUG, INBUG bit. Opcode for TRET is 0x00E1. BDM registers ------------- BDM is controlled by one main register and three shadow registers. Main control register of BDM is DEBUG register at address 0xFD4 (notice gap at SFR map in all PIC18F devices). DEBUG (0xFD4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INBUG FRZ SSTP SHDW BRB7 BRB6 BTS7 BTS6 INBUG - this readable bit is set in debug mode and clear during executing user code FRZ - this bit is clear by default. Setting this bit enables peripheral freezing in debug mode SSTP - this bit is clear by default. Setting this bit enables single step operation. After return from debug mode, only one instruction will be executed before entering debug mode again. SHDW - this bit is clear by default. Setting this bit enables shadow registers BDMSR0, BDMSR1, BDMSR2 BRB7 - bit to manipulate RB7 in debug mode, without affecting actual content of POR TB,7 register BRB6 - bit to manipulate RB6 in debug mode, without affecting actual content of PORTB,6 register BTS7 - bit to manipulate TRISB7 in debug mode, without affecting actual content of TRISB,7 register BTS6 - bit to manipulate TRISB6 in debug mode, without affecting actual content of TRISB,6 register There are also at least three shadow registers, accessible only when DEBUG,SHDW bit is set: BDMSR2 (0xFB9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? BKA19 BKA18 BKA17 BKA16 BDMSR1 (0xFB8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKA15 BKA14 BKA13 BKA12 BKA11 BKA10 BKA9 BKA8 BDMSR0 (0xFB7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKA7 BKA6 BKA5 BKA4 BKA3 BKA2 BKA1 BKA0 BKA[19..0] forms 20 bit wide register, holding address of breakpoint. When PC=BKA, BDM takes control and debug mode is entered. ? fields are bits with unknown meaning, for now. Don't touch it. Communication with target device -------------------------------- All communication with target device is done by RB6 and RB7 lines and MCLR. Before entering debug mode, target device (TD) has to be programmed using ICSP, so debugger implemntation has to contain also programmer implementation. Except of user code, TD has to have two additional regions programmed - debug vector and debug executive, for PIC18Fxxxx devices. For PIC18FxxJxx devcies, there are differences, covered later. Debug executive (DE) is program, which takes control after entering debug mode by BDM in TD. Its function is to communicate with debugger by RB6 and RB7 lines, using custom protocol. BDM does not support this communication by any way other than providing bits to manipulate with those pins and appropriate TRIS bits (see description of DEBUG register). Best place for DE is last few pages of FLASH memory, in order to not interfere with user program. Properly written DE can be smaller than 512B, or 256 program words. Debug vector (DV) is single instruction to redirect program execution into DE after entering debug mode. Memory region where DV resides, is ordinary FLASH block and must be erased and written in the same way as any other FLASH block. For PIC18FxxJxx devices, region where DV resides, is larger and complete DE will fit here (If you look at MPLAB help, you can find table about which resourced are consumed in order to use ICD. Those ones with no FLASH consumed allow to put complete DE into DV region). After programming (using ICSP) user code, DE and DV, MCLR has to be toggled to start execution of code. After reset, BDM takes control, forces PC to DV, where it executes instruction to enter DE in FLASH memory. Here is the point, where DE takes control and is fully responsible for communication with debugger. The same process is executed after introducing falling edge at RB6 pin, while running user code (this can be used to stop program flow). In all cases, except of POR or MCLR RESET, before forcing PC to DV, current PC value s saved on stack and stack pointer is incremented, so that TRET instruction can revert PC value to point before execution interrupt. After POR or MCLR reset, stack pointer is equal to zero, so TRET instruction can't do this. Because of this, DE has to check stack pointer and when it is equal to zero (situation after MCLR or POR reset), it has to increase stack pointer and clear TOSL, TOSH and TOSU registers - this forces PC return to correct address 0 after leaving DE. It is good idea to use both RB6 and RB7 pins to create simple bidirectional synchronous (in order to be not dependant on target clock) serial protocol. From protocol point of view, DE could be quite simple. Reading and writing registers, FLASH and EEPROM should be implemented, along with setting breakpoint address or single stepping. On debugger side, it is a bit more complicated. What is missing here -------------------- As a lot of those information are guessed only, it is incomplete. For example, I don't know how to set more than one breakpoint - for devices which allow more than one breakpoint. If you have further information to improve this document, contact me. How to... I made small handheld debugger which allows editing source code, assembling it, flashing into program memory and debugging of PIC18xxxx, PIC18FxxJxx and PIC18FxxKxx devices. It employs all priciples described above, you can find also source codes for both DE and debugger part. Updated 18.3.2011 Entry: I2C arbitration Date: Mon Mar 21 09:04:41 EDT 2011 How does send/receive arbitration work on I2C? According to [1], usually devices take on a single master or slave role, but they can switch between read and write. Looking at the PICkit spec PICkit2SourceGuidePCv2-52FWv2-32.pdf from [2] it seems that I2C uses the ICD AUX(6) pin which is normally LVP. [1] http://en.wikipedia.org/wiki/I2c [2] entry://../staapl/20080818-165846 Entry: Next hardware projects Date: Mon Mar 21 09:38:00 EDT 2011 1. Synth controller / calibration. This is a circuit implementing a collection of haptic-band (< 200Hz) DACs using class-D drivers connected to exponential sawtooth VCOs, using square wave frequency feedback for calibration. Requirements: - Staapl multi-PIC monitor, i.e. I2C - USB for monitor + MIDI 2. Staapler. This is a circuit implementing an alternative programmer that works better with Staapl. This could use PK2 firmware but probably needs dedicated firmware to be effective. Will support only limited set of chips since it's probably best to incorporate virgin chip programming. To get this going, make a test board with 2 PICS, one to act as a programmer, and one as a slave. A simple circuit is possible if I use LVP on the slave PIC. A PK2 with modified firmware is probably best, but is more work to get going. A PK2 with v2 firmware should be enough. Here, using the standard 20bit protocol is probably best, as it's best supported. Last time I got stuck on getting the bit-banged async serial to work reliably. Components: - USB driver - I2C monitor It looks like the USB driver is going to have the highest payoff, as it would avoid the necessity of building new boards. It also seems like the most work. Reusing a PK2 v2 and sticking to something that can use the programming protocol seems to be the best approach. So let's revive the pk2 code first. Entry: Rigol DS1052E Date: Fri Mar 25 22:44:18 EDT 2011 The scope arrived. I payed about $400. Dollar/Euro is at 1.4 today so this is really quite a deal. Played with it a bit, and it seems to be quite nice. First thing I did (after FFTs on 60Hz mains) is to hook it up to the serial port of my PIC18F2550 setup to test the trigger mode. I noticed some 100ns rise time spikes of about 1.3V. What's that about? They consistently happen at regular intervals after the normal serial transitions (baud at 230k4). Cable reflections? Looks like it. Distance of the spikes is 188us. Entry: Rigol remote control using usbtmc Date: Sat Mar 26 16:07:07 EDT 2011 Quite straightforward. It's almost like a serial terminal, but usbtmc seems to be message based, and there is timing information. However using the character device, all of the complexities of the usbtmc protocol are hidden. I'm using this[1] quick-hack to query the device: tmc # send command tmc -r # .. and print reply Useful commands *IDN? Identitiy *RST Reset :RUN Start capturing / wait for trigger :STOP Stop capturing :AUTO Autoset :TRIG:EDGE:SWE SING Single shot :TRIG:EDGE:SWE AUTO Continuous display To get waveform data: :WAV:POIN:MODE NOR :WAV:DATA? CHAN1 That first command I got from here[2]. I didn't find it in the manual. The second one only makes the 2.05 SP2 crash. I wonder how to download the entire data buffer.. Manual doesn't seem to be complete. Btw, it's great to have [1] sending ":RUN" to the scope to arm the trigger, with that command bound to a key in emacs. [1] http://zwizwa.be/darcs/pool/src/tmc.c [2] http://www.cibomahto.com/2010/04/controlling-a-rigol-oscilloscope-using-linux-and-python/ Entry: Jeri's toy stories Date: Mon Mar 28 15:10:16 EDT 2011 In the toy industry, it's not time-to-market but cost that's most important according to Jeri Ellsworth[1]. [1] http://www.theamphour.com/2011/03/21/the-amp-hour-35-the-ternary-tussle/ Entry: Electronics: There Is No Abstraction Date: Sun Apr 10 16:56:51 EDT 2011 Amanda Wozniak: Hardware Will Cut You[1]. A very true story about how electronics is not programming. The one that hit it on the head was: there is no abstraction. You have to think about everything all the time. [1] http://www.eevblog.com/2010/11/08/hardware-will-cut-you/ Entry: El-cheapo modular synth board layout Date: Sat Apr 23 00:48:38 EDT 2011 The missing link: a no-brainer connection strategy. When using a current in, voltage out approach, many circuits become simpler, and you get free fixed-gain configurability if you allow the resistors to be socketed. I.e. using a 3-hole configuration like: in Ra Rb o--o o--> vground A wire can be plugged into the input, and a gain resistor can be plugged across Ra/Rb. This layout has the advantage that it can accomodate both a proto-board and the final layout (simply hard-wire the connection and the scaling resistor). To make it even simpler the resistor can be omitted and be made part of the "patch cable", however that doesn't work well for simple fixed circuit boards. So a 3x1 100 mil through-hole array seems best. If all sockets are made female, patch wires can be made cheap (just stripped wire) and resistors go straight into the sockets. Entry: One circuit a day Date: Sat Apr 23 01:30:52 EDT 2011 I'd like to get out of cargo cult component fondling MO and into building working circuits. The following things I want: - Guitar headphone preamp. - El-cheapo modular synth. Both should run on the tiny perfboard I got, using standard TL072 opamps, of off 9V batteries. Entry: Opening up BeBook e-reader Date: Wed Apr 27 19:28:41 EDT 2011 - Take out the 4 cylindrical rubber plugs that cover 4 screws on the back. Remove 4 screws + one for the battery holder. - Use some sticky gum to temporarily attach the battery to the board otherwise it's dangling. - Take off the back cover by prying it open at the USB connector, then go around. - Serial console is at J8. Center is ground, closest to the label is TX the other end is (probably) RX. - The distance between the pads is not quite 100mil, more like 2mm. I used a 3-prong SIP socket and bent the wires a bit, then use jumper wires into a TTL serial female header plug. - The baud rate is 115200. - Plug in USB to prevent it from going to sleep. OK U-Boot 1.1.6-g1b97c629-dirty (Aug 24 2009 - 14:27:37) for SMDK2416 CPU: S3C2416@400MHz Fclk = 800MHz, Hclk = 133MHz, Pclk = 66MHz Board: SMDK2416 Mobile SDRAM DRAM: 32 MB NAND: 512 MB (Memory Based BBT Enabled) *** Warning - bad CRC or NAND, using default environment In: serial Out: serial Err: serial Battery Power : 4.01v 8 Gray Level Screen Supported! Hit any key to stop autoboot: 0 NAND read: device 0 offset 0x200000, size 0x1c0000 1835008 bytes read: OK Boot with zImage Starting kernel ... Uncompressing Linux....................................................................... done, booting the kernel. Linux version 2.6.21.5-cfs-v19 (maoyk@celling) (gcc version 4.0.0) #507 Wed Nov 4 13:30:36 CST 2009 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 Machine: SMDK2416 Ignoring unrecognised tag 0x00000000 Memory policy: ECC disabled, Data cache writeback CPU S3C2416 (id 0x32450003) S3C24XX Clocks, (c) 2004 Simtec Electronics S3C2416: mpll on 800.000 MHz, cpu 400.000 MHz, mem 133.333 MHz, pclk 66.666 MHz S3C2416: epll on 192.000 MHz, usb-bus 48.000 MHz CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets Built 1 zonelists. Total pages: 8128 Kernel command line: noinitrd root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0 mem=32M irq: clearing subpending status 00000402 irq: clearing subpending status 00000002 PID hash table entries: 128 (order: 7, 512 bytes) timer tcon=00500000, tcnt 28af, tcfg 00000f00,00000000, usec 00007ae2 Console: colour dummy device 80x30 Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory: 32MB = 32MB total Memory: 30120KB available (1936K code, 291K data, 92K init) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 S3C2410 Power Management, (c) 2004 Simtec Electronics S3C2416: Initialising architecture S3C2416: IRQ Support S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics DMA channel 0 at c2800000, irq 88 DMA channel 1 at c2800100, irq 89 DMA channel 2 at c2800200, irq 90 DMA channel 3 at c2800300, irq 91 DMA channel 4 at c2800400, irq 92 DMA channel 5 at c2800500, irq 93 DMA channel 6 at c2800600, irq 99 DMA channel 7 at c2800700, irq 100 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered NetWinder Floating Point Emulator V0.97 (double precision) JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. io scheduler noop registered io scheduler anticipatory registered (default) io scheduler deadline registered io scheduler cfq registered S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics Founded postion :[11] Founded postion :[11] s3c2440-uart.0: s3c2410_serial0 at MMIO 0x50000000 (irq = 70) is a S3C2440 s3c2440-uart.1: s3c2410_serial1 at MMIO 0x50004000 (irq = 73) is a S3C2440 s3c2440-uart.2: s3c2410_serial2 at MMIO 0x50008000 (irq = 76) is a S3C2440 loop: loaded (max 8 devices) wake enabled for irq 50 wake enabled for irq 16 wake enabled for irq 17 wake enabled for irq 18 wake enabled for irq 19 wake enabled for irq 58 wake enabled for irq 59 wake enabled for irq 51 PPP generic driver version 2.4.2 PPP Deflate Compression module registered s3c2410 NOR-Flash Driver, (c) 2004 Simtec Electronics s3c2410-nor: Found 1 x16 devices at 0x0 in 16-bit bank Amd/Fujitsu Extended Query Table at 0x0040 number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. Creating 1 MTD partitions on "s3c2410-nor": 0x00000000-0x00200000 : "Boot loader" S3C NAND Driver, (c) 2007 Samsung Electronics S3C NAND Driver is using hardware ECC. NAND device: Manufacturer ID: 0xad, Chip ID: 0xdc (Hynix NAND 512MiB 3,3V 8-bit) Scanning device for bad blocks Creating 6 MTD partitions on "NAND 512MiB 3,3V 8-bit": 0x00200000-0x00400000 : "KERNEL" 0x00400000-0x00a00000 : "BASEFS" 0x00a00000-0x07d00000 : "ROOTFS" 0x07d00000-0x07e00000 : "LOGO" 0x07e00000-0x08000000 : "USERDATA" 0x08000000-0x1f000000 : "STORAGE" Loaded s3c-udc version Nov 4 2009 S3C24XX RTC, (c) 2004,2006 Simtec Electronics res->start : 57005000 res->end : 0<6>s3c2410-rtc s3c2410-rtc: rtc disabled, re-enabling s3c2410-rtc s3c2410-rtc: rtc core: registered s3c as rtc0 i2c /dev entries driver s3c2410-i2c s3c2410-i2c: slave address 0x10 s3c2410-i2c s3c2410-i2c: bus frequency set to 9 KHz s3c2410-i2c s3c2410-i2c: i2c-0: S3C I2C adapter wake enabled for irq 48 [s3c_hsmmc_probe]: s3c-hsmmc.0: at 0xc286c000 with irq 37. clk src: hsmmc Registered led device: nand-green-led-data Registered led device: nand-red-led-data Registered led device: mmc-green-led-data Registered led device: mmc-red-led-data Registered led device: charge-green-led-da Registered led device: charge-red-led-data Registered led device: lcd-green-led-data Registered led device: lcd-red-led-data Advanced Linux Sound Architecture Driver Version 1.0.14rc3 (Wed Mar 14 07:25:50 2007 UTC). smdk_audio_matchdev: dev=c020d948 ALSA device list: #0: S3C2410 TLV320 TCP cubic registered NET: Registered protocol family 1 NET: Registered protocol family 17 s3c2410-rtc s3c2410-rtc: hctosys: invalid date/time VFS: Mounted root (cramfs filesystem) readonly. Freeing init memory: 92K init started: BusyBox v1.8.2 (2008-12-03 22:38:29 CST) starting pid 238, tty '': '/etc/init.d/rcS' Make /etc writeable Remounting /etc as writeable ...... DONE vm.dirty_writeback_centisecs = 10 vm.dirty_expire_centisecs = 10 Mounting local filesystems... Starting system message bus: [ $OK ] starting pid 279, tty '': '/bin/autologin' Welcome to jinke ebook system... login[279]: root login on 'ttyS0' /bin/dbus-launch --exit-with-session Startx.... # Sending signal PowerChange with value PowerLevel4 nxclient: retry connect attempt 1 FAT: utf8 is not a recommended IO charset for FAT filesystems, filesystem will be case sensitive! open file:/root/appdata/fontlib.conf error wake enabled for irq 46 wake disabled for irq 46 wake enabled for irq 46 Stopping tasks ... done. Suspending console(s) s3c2410_pm_enter(3) s3c2410_sleep_save_phys=0x3167be5c Leaving IRQ 16 (pin 160) enabled Leaving IRQ 17 (pin 161) enabled Leaving IRQ 18 (pin 162) enabled Leaving IRQ 19 (pin 163) enabled Leaving IRQ 48 (pin 164) enabled Disabling IRQ 49 (pin 165) Leaving IRQ 50 (pin 166) enabled Leaving IRQ 51 (pin 167) enabled Disabling IRQ 57 (pin 197) Leaving IRQ 58 (pin 198) enabled Leaving IRQ 59 (pin 199) enabled sleep: irq wakeup masks: bffffff0,ffff3f2f [1] http://delicious.com/doelie/bebook [2] http://openinkpot.org/wiki/Device/V5/SerialPort Entry: Low power PIC tips Date: Thu May 19 23:07:08 CEST 2011 The PIC datasheets clearly state that non-digital signals (around 1/2 Vcc) should never be connected to a digital input to avoid linear biasing of the CMOS input state which draws a lot of power. However [1] mentions on page 2-4 that: "Sometimes it is appropriate and possible to configure digital inputs as analog inputs when the digital input must go to a low power state." Which vaguely implies that analog inputs consume less power than digital ones. If the inputs are logic-level (i.e. not 1/2 Vcc) then I doubt this is true. Maybe it's a safety measure in case the input starts floating? Or is it about the leak current of a CMOS input stage vs. that of an analog input stage? What do uC analog inputs look like? Are they comparator inputs? Those would be differential pairs. What about their bias current? Ha! It's not the ADC input that counts, but the analog MUX. I suppose the ADC input stage is simply off when not converting, not drawing any leakage current. For the PIC input pints, the only difference between analog and digital mode is that digital mode has power to the digital input buffer, so always uses more power (input buffer leakage). [1] http://ww1.microchip.com/downloads/en/DeviceDoc/01146B_chapter%202.pdf Entry: PIC ADC Date: Tue Jul 12 13:56:26 CEST 2011 When changing ADC channel (amux switch), it is necessary to wait a bit for the holding cap to charge. Entry: WDTV Live Date: Mon Sep 19 20:27:31 EDT 2011 Console connector: -- ----- -- | . . . . | | | --+-+-+-+-- 5 R T G V X X N D [1] http://www.legitreviews.com/article/1118/2/ Entry: Hooking up L78L33 3v3 regulator from 9V Date: Tue Sep 27 11:55:35 EDT 2011 See datasheet L78L33[1]. BOTTOM VIEW _________ \ 1 2 3 / \_____/ 1 = V_OUT 2 = GND 3 = V_IN These are from the test circuit. Not sure if necessary: C_IN = 0.33uF C_OUT = 0.100uF I' just put 2 1uF elcos on either side. Plugged it in wrong first (pic says bottom view!). It started smelling, got pretty hot. Still works after turning it around. [1] http://www.decelectronics.com/html/PDF/L78L33.pdf Entry: PICkit v2 wiring Date: Tue Sep 27 15:01:14 EDT 2011 >1 MCLR white 2 VDD red 3 GND black 4 PGD blue 5 PGC green 6 PGM ? [1] http://www.ianstedman.co.uk/Projects/TK3_PICKit2_adaptor/tk3_pickit2_adaptor.html Entry: Serial port hardware flow control Date: Wed Oct 19 12:38:02 EDT 2011 Something which has always confused me. See wikipedia[1]. For a null modem connection which seems to be my only use case, simply connect the RTS out of one side to the CTS in of the other and vice versa. /CTS input: other side ties low to indicate it can receive more data /RTS output: we tie low when we can receive more data. So what about DTS / DTR? It seems that these are connected to RTS and CTS for a non-symmetric (non-null modem) line. [1] http://en.wikipedia.org/wiki/RS-232_RTS/CTS#RTS.2FCTS_handshaking Entry: slow, synchronous bi-directional protocol Date: Sun Nov 6 13:15:45 EST 2011 I need something to connect 2 slow devices, meaning that neither end has a timing restriction and can take as long as it pleases inbetween protocol phases. This needs 4 lines on both ends, cross wired + ground. Let's do DR = data ready RA = read ack Dx = data out/in Timing diagram ___ ___ DR __| |___| |_____ DO /// /// ___ ___ RA ____| |___| |___ DI /// /// The problem with this is that it is not symmetric. It would be simpler to make it fully ping-pong and only trigger on edges: every transition on the sync line indicates that the next bit is valid. Here 'X' means a data transition, all the other states are valid. ___ ___ DR __| |___| |_____ DO 0 X 1 X 2 X 3 X 4 ___ ___ RA ____| |___| |___ DI 0 X 1 X 2 X 3 X 4 This is fully symmetric because only the edges count, not the levels. In receive mode, we wait for a clock edge, then read the data, write our data and flip our clock then switch back to receive mode. Once this is locked we have a bi-directional bit stream that can go arbitrarily slow. It probably needs some logical protocol on top of that for synchronization, to allow insertion of idle bit patterns. So how to start it up? Someone has to send the first edge, and it needs to know that the other side will see that edge, meaning it was listening. From there on it is straightforward, but that first start doesn't seem so simple. It needs extra starting conditions: - Who will send the first bit. This creates the initial a-symmetry to get the loop going: one will wait for reception and the other will cause the first write. - What edge will be used for the first bit. This is necessary to initialize the edge detector (differentiator). Entry: High-school electronics vocation Date: Thu Jan 12 11:51:09 EST 2012 Looks like I have the chance to participate in a High-school vocational electronics program. What to teach? The most useful seems to be Arduino, since it's gotten quite popular. I've never used it, so here it goes. I need to order an Arduino board, so want to know which one to order. There seem to be several varieties. Which one is best? - Latest: Uno[1] ATmega328[5] (main) + ATMEGA8U2[6] as USB serial converter. - Previous: Duemilanove[3]. ATmega168 or ATmega328 + FTDI. Others are here[4]. I don't see a point in getting any of the bigger ones, so it seems Uno is best. I got 2 on eBay here[2]. Also, some chips that are not code-compatible, but have the same header layout: - LeafLabs Maple r5 [1] http://arduino.cc/en/Main/arduinoBoardUno [2] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=320828429181#ht_830wt_1112 [3] http://arduino.cc/en/Main/arduinoBoardDuemilanove [4] http://arduino.cc/en/Main/Boards [5] http://www.atmel.com/dyn/products/product_card.asp?part_id=4720 [6] http://www.atmel.com/dyn/products/product_card.asp?part_id=4600 Entry: LeafLabs Maple r5 Date: Thu Jan 12 12:52:19 EST 2012 ( TL;DR : Don't use the IDE. Follow instructions in [3]. ) I had some trouble with one particular usb port. Plugging it in a powered hub seems to solve the issue. Here's how it registers. [5020582.977878] usb 1-4.1.4.2: new full speed USB device using ehci_hcd and address 100 [5020583.087990] usb 1-4.1.4.2: New USB device found, idVendor=1eaf, idProduct=0003 [5020583.087993] usb 1-4.1.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [5020583.087995] usb 1-4.1.4.2: Product: Maple 003 [5020583.087997] usb 1-4.1.4.2: Manufacturer: LeafLabs [5020583.087998] usb 1-4.1.4.2: SerialNumber: LLM 003 [5020585.575876] usb 1-4.1.4.2: USB disconnect, address 100 [5020585.793800] usb 1-4.1.4.2: new full speed USB device using ehci_hcd and address 101 [5020585.906534] usb 1-4.1.4.2: New USB device found, idVendor=1eaf, idProduct=0004 [5020585.906537] usb 1-4.1.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [5020585.906539] usb 1-4.1.4.2: Product: Maple [5020585.906541] usb 1-4.1.4.2: Manufacturer: LeafLabs [5020586.229291] cdc_acm 1-4.1.4.2:1.0: ttyACM0: USB ACM device [5020586.230219] usbcore: registered new interface driver cdc_acm [5020586.230221] cdc_acm: v0.26:USB Abstract Control Model driver for USB modems and ISDN adapters I'd like to find out the following: - How to use the IDE[1] - How to bypass the IDE and build an eCos-based image and load it in DFU mode. First, switching to DFU mode is done by holding the button through a reset. Doesn't seem to work, neither with reset nor power cycle (unplug/replug USB). Doesn't seem to work on 64bit. tom@zoo:/opt/xc/maple$ ./maple-ide java.lang.UnsatisfiedLinkError: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so 32 (Possible cause: architecture word width mismatch) thrown while loading gnu.io.RXTXCommDriver Exception in thread "main" java.lang.UnsatisfiedLinkError: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so: /opt/xc/maple-ide-v : wrong ELF class: ELFCLASS32 (Possible cause: architecture word width mismatch) at java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.lang.ClassLoader.loadLibrary0(ClassLoader.java:1750) at java.lang.ClassLoader.loadLibrary(ClassLoader.java:1675) at java.lang.Runtime.loadLibrary0(Runtime.java:840) at java.lang.System.loadLibrary(System.java:1047) at gnu.io.CommPortIdentifier.(CommPortIdentifier.java:123) at processing.app.Editor.populateSerialMenu(Editor.java:795) at processing.app.Editor.buildToolsMenu(Editor.java:612) at processing.app.Editor.buildMenuBar(Editor.java:413) at processing.app.Editor.(Editor.java:187) at processing.app.Base.handleOpen(Base.java:608) at processing.app.Base.handleOpen(Base.java:573) at processing.app.Base.handleNew(Base.java:475) at processing.app.Base.(Base.java:245) at processing.app.Base.main(Base.java:149) So, running on 32bit with sun java 6 it comes up, but is hardly usable. The UI seems to be full of bugs... Though this could be Java interacting with XMonad, which I've seen do weird things before. Let's switch to emacs and command line tools. Seems that the only thing the IDE does is compile and upload. See reference/unix-toolchain.html [3] for info on using libmaple without the IDE. Tested: the first time I got a segfault in the dfu upload as part of "make install". After that it seemed to work. Looks like the rest should be straightforward: - Figure out the memory layout for the DFU image. - Figure out the upload protocol, i.e. how does it actually switch to DFU? - Does eCos have drivers for this chip? STM32F103RBT: Maple. STM32F103ZET6: eCos port for the STM3210E-EVAL[4] board. These seem to be similar enough to at least give it a try. Essential devices seem to be supported: tom@zoo:~/ecos-build/src/cvs/packages/devs$ find -name '*stm32*' |grep cdl ./flash/cortexm/stm32/current/cdl/flash_stm32.cdl ./usb/cortexm/stm32/current/cdl/usb_stm32.cdl ./spi/cortexm/stm32/current/cdl/spi_stm32.cdl ./adc/cortexm/stm32/current/cdl/adc_stm32.cdl ./serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl ./wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl Next: - build eCos config - port LwIP to maple? [1] http://leaflabs.com/docs/maple-ide-install.html#maple-ide-install-linux [2] http://wiki.openmoko.org/wiki/Dfu-util [3] http://leaflabs.com/docs/unix-toolchain.html [4] http://www.st.com/internet/evalboard/product/204176.jsp Entry: Linux host for USB debugging Date: Thu May 17 13:20:47 EDT 2012 I'm writing firmware for a USB device. It would be useful to now be able to run a kernel inside a debugger to see what's going on, and maybe to freeze the enumeration process. I don't want to do this on my development host because I might crash the kernel. I was thinking user mode linux or KVM for debugging, but it doesn't look like that's going to work. It seems to me that all emulation will just pass USB stuff to the hosts' usb layer, and that's exactly what I'm trying to debug. Maybe its best to do this on a real host with some kind of kernel debugger or at least a bunch of logging? This needs: - A real host with usb subsystem as modules - Probably compiler on the real host I have an old dell laptop to set this up. Let's give it a try. First, lets backup. apt-get source linux-2.6 Once configured, to build only a single subdirectory, use. make modules SUBDIRS=drivers/the_module_directory I don't know how to configure a linux tree though.. maybe just building it with kpkg-deb ? I'm just using "make menuconfig" default now. make oldconfig make prepare make modules SUBDIRS=drivers/usb/host I have both uhci_hcd and ehci_hcd. Which is it? Stuff seems to work without ehci_hcd. It seems to work with only uhci_hcd, USB 1.1 drivers/usb/host/uhci-hcd.c The error messages like: [ 8007.022046] usb 1-1.4: device descriptor read/64, error -71 come from drivers/usb/core/hub.c Maybe it helps plugging it in directly to the 64bit host? Entry: USB debugging Date: Fri May 18 14:01:38 EDT 2012 broebel:~# mount -t debugfs none_debugs /sys/kernel/debug broebel:~# sudo modprobe usbmon broebel:~# cat /sys/kernel/debug/usb/usbmon/1u | tee /tmp/usbmon_1u.log Entry: USB protocol info Date: Sat May 19 14:54:26 EDT 2012 A 0 is introduced after 6 consecutive one bits to ensure enough transitions. To decode this, just do the reverse: if 6 consecutive one bits are received, drop the following zero. If 7 consecutive ones are detected a bit stuffing error is raised an the packet is discarded. A packet on the wire is a NRZI encoding of a packet, prefixed with a clock sync pattern. See 7.1.9 in USB1.1 spec [1]. From 8.4.5.4 in [1] it says that SETUP is a special kind of OUT that resets the data sync. SETUP token is always followed by a DATA token. From 8.5.2 in [1]: Control Transfers Control transfers minimally have two transaction stages: Setup and Status. Setup is SETUP + DATA0. The Status stage is delineated by a change in direction of data flow from the previous stage and always uses a DATA1 PID. The terms are a bit confusing: transaction, sequence, token, .... Anyhow, it seems that I don't need to care about ACK. So, a "stage" is actually two tokens: SETUP, DATA0 OUT, DATAx IN, DATAx The SETUP, OUT, IN tokens are always sent by the host. The DATAx tokens are sent by the host if preceded by SETUP and OUT, or by the device is preceeded by IN. ( On the PIC, these stages are atomic. ) Questions: - In figure 8-12 [1], does a DEVICE GET_DESCRIPTOR request have a data stage? I.e. is it a Control Read or a No-Data control - Is the Status IN always empty, or can it have a payload? [1] http://esd.cs.ucr.edu/webres/usb11.pdf Entry: OLS upgrade Date: Sun May 20 20:18:00 EDT 2012 Installing new OLS firmware from: http://github.com/downloads/GadgetFactory/OpenBench-Logic-Sniffer/ols-0308.tgz This doesn't seem right: [294392.178180] usb 4-1.4: new full speed USB device using ehci_hcd and address 18 [294392.274850] usb 4-1.4: New USB device found, idVendor=04d8, idProduct=fc90 [294392.274861] usb 4-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [294392.274868] usb 4-1.4: Product: Diolan [294392.274873] usb 4-1.4: Manufacturer: Diolan [294392.278940] generic-usb 0003:04D8:FC90.0004: hidraw2: USB HID v1.01 Device [Diolan Diolan] on usb-0000:00:16.2-1.4/input0 Ah, sudo make me a sandwich.. Tested with UART. Seems to work well. Entry: anti-aliased Java fonts Date: Sun May 20 20:37:12 EDT 2012 -Dawt.useSystemAAFontSettings=on -Dswing.aatext=true [1] http://stackoverflow.com/questions/179955/how-do-you-enable-anti-aliasing-in-arbitrary-java-apps Entry: Rigol firmware 2.05 SP2 hacked Date: Mon May 21 01:13:22 EDT 2012 To make it downgrade, it's enough to change the version in the firmware header, see [2]. Old headers: HEX Address: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 --------------------------------------------------------------------------- v2.05.01.00: 44 53 31 30 30 30 45 20 20 20 82 85 84 88 C3 7B 47 92 39 C8 7E v2.05.01.02: 44 53 31 30 30 30 45 20 20 20 82 85 84 82 8B B8 96 41 63 FF 33 v2.05.02.00: 44 53 31 30 30 30 45 20 20 20 82 85 82 88 C0 7E D7 6A 15 B6 B6 --------------------------------------------------------------------------- Fields: |<------ Std. header -------->|<-FW rev.->|<-?->|<- CRC32 ->|??| --------------------------------------------------------------------------- v2.05.02.01: 44 53 31 30 30 30 45 20 20 20 __ __ __ __ __ __ __ __ __ __ __ --------------------------------------------------------------------------- Byte(00..09) = Std. header = 0x44533130303045202020 Byte(0A..0D) = FW rev. = 0x________ Byte(0E..0F) = ? = 0x____ Byte(13..10) = CRC-32(00..0F) = 0x________ Byte(14) = ?? = 0x__ Filled in (more info see [2]): HEX Address: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 --------------------------------------------------------------------------- v2.05.02.01: 44 53 31 30 30 30 45 20 20 20 82 85 82 84 C3 7B FF 34 48 E4 7E Fields: |<------ Std. header -------->|<-FW rev.->|<-?->|<- CRC32 ->|??| 2.05.02.01.header checksums: CRC32: 719FAB26 MD5: B058467F61FF6D62712A64B3F8E8D0F8 SHA-1: 54217AFA199A05BBFBC908CE71DD2039D7C1F78A I found firmware here [3][4]. tom@zoo:/opt/xc/rigol/Firmware v2.02 SP2 (2.02.02.00)$ md5sum DS1000EUpdate.RGL 272086b2037231c62446617436544a77 DS1000EUpdate.RGL Google link[5] for the MD5. Also, changing the model to DS1152E once 2.02 is loaded sets BW limit to 150MHz[6]. [1] http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&p=900066 [2] http://www.eevblog.com/forum/blog-specific/changing-the-rigol-ds1052e-to-ds1102e-using-usb-the-dummy-guide/msg42404/#msg42404 [3] http://www.mediafire.com/?89qmofj54tgw7ak [4] http://www.eevblog.com/forum/blog-specific/changing-the-rigol-ds1052e-to-ds1102e-using-usb-the-dummy-guide/msg70378/#msg70378 [5] http://www.google.com/search?q=272086b2037231c62446617436544a77 [6] http://www.eevblog.com/forum/general-chat/ds1052e-up-to-150mhz/ Entry: Hex editors Date: Mon May 21 01:38:52 EDT 2012 [1] http://stackoverflow.com/questions/839227/how-to-edit-binary-file-on-the-unix-systems Entry: Manually decoding USB packet Date: Tue May 22 23:09:16 EDT 2012 Using the logic analyzer, sampled at 100MHz. What's weird is those last 2 bits. All packets seem to have that. D+ 1010101110010011101000110110010000 D- 0101010001101100010111001001101100 ?? Entry: TotalPhase Beagle Intel EHCI Issue Date: Fri Jun 15 19:26:10 EDT 2012 00:12.2 USB Controller: ATI Technologies Inc SB700/SB800 USB EHCI Controller My device seems to be affected by this issue[1]. Plugging the Beagle into a different bus solves it. [1] http://www.totalphase.com/support/kb/10049/ Entry: Belkin Share Max N300 UART Date: Fri Jul 6 13:04:58 EDT 2012 I'm opening it up to find the UART. Remove the 2 torx screws in the foot, pry open the case along the slit. This removes one plastic cover exposing the front of the boared. Remove 4 philips screws to remove the board after removing the other cover. From inspection, it's probably J3, which has a 4 pin header: 1 VCC 2 TX 3 RX 4 GND GND based on trace: pin is connected to ground plane. From there TX gave something on logic analyzer. The RX/VCC is a guess based on the traces I can see going to the chip: only 2/3. Captured on the Logic analyzer is "Decompressing..." Autobaud rate is 114285 ~ 115200. Voltage is 3.3V Entry: Serial 3.5mm jack Date: Sun Jul 8 17:03:10 EDT 2012 The TTL-232R-3V3-AJ FTDI cable[1] might be the best option for adding a serial console to a consumer router box, as they require just a round hole to be added to the enclosure. TIP = TX RING = RX SLEEVE = GND That's a nice mnemonic :) [1] http://www.mouser.com/ProductDetail/FTDI/TTL-232R-3V3-AJ/?qs=Xb8IjHhkxj6MWaLhwTpkXw%252bfeNsBA0WO [2] http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf Entry: Workig with buggy USB devices Date: Wed Aug 1 10:42:23 EDT 2012 I have a Segger Atmel ARM debugger and a PICKit2 that both can get stuck, requiring a unplug/replug cycle. This makes it hard to automate testing. How to fix? Some possible solutions: - Small circuit that cuts USB power - A linux host that exports both devices to the network and can be reset or power-cycle. Trouble is that the Segger GDB is closed source, so the host needs to be a linux box. Entry: GDB hooks Date: Wed Aug 1 11:03:34 EDT 2012 I'm using a single breakpoint to do "hot patching" of an embedded application. This works well if the sequence of "continue" commands are run from a "while" loop. Trouble is that I want to hide this a bit more and call "continue" from a hook. Something tells me this is not a good idea, causing recursion stack overflow. That actually didn't happen, but I did get problems with malloc() which is used by GDB to insert things like strings into the target's memory. Entry: disabling emacs gud popup windows Date: Wed Aug 1 13:52:12 EDT 2012 (defadvice pop-to-buffer (before cancel-other-window first) (ad-set-arg 1 nil)) (ad-activate 'pop-to-buffer) ; Doesn't do what i think it does.. [1] http://stackoverflow.com/questions/812192/emacs-preventing-gud-pdb-from-controlling-windows Entry: Trickle charge Date: Wed Aug 8 20:28:33 EDT 2012 5mA current source -> NiMH recover after fast charging Entry: Stackable headers Date: Wed Sep 19 17:32:48 CEST 2012 Where to buy? Volume prices: Adafruit: 100 sets: 1.56 ebay/nooelec: 25 sets: 1.01 (/ (+ 9.25 11.50 1.75 2.75) 25) Niagara Falls ebay/zangyun727: 20 sets: 1.08 (/ 21.50 20) ebay/tenovo2010: 25 sets: 0.88 (/ 21.90 25) Entry: FreeRTOS Date: Sat Sep 29 13:26:56 EDT 2012 Would like to try FreeRTOS[1]. Ports of interest: - dsPIC[2], main reason this is interesting: available in DIP packages + DSP ops. - SAM7[3] [1] http://www.freertos.org [2] http://www.freertos.org/portpic24_dspic.html [3] http://www.freertos.org/a00090.html#ATMEL Entry: dsPIC Date: Tue Oct 2 11:42:51 EDT 2012 Many things are pointing into one direction, the dsPIC30F2012[1] which I've ordered several years ago when I was still thinking about porting Staapl[2] to dsPIC. This probably won't happen, as Staapl by itself is a time sink and another world in some sense. It's main use is for writing interfacting components (i.e. USB interface, knobs & buttons). I need a platform for Haskell/C/DSP stuff and apart from plain PC with Pd, it seems that the dsPIC might be a good candidate: - More traditional RISC register machine - GCC available - FreeRTOS available - Small DIP packaging - A simple DSP (Single cycle MAC, fixed point multiplication, bit rev addr) EDIT: Compilers are not free? I have an early version of dsPIC GCC, C30 version 3.01 The Microchip website is a bit confusiong. It seems that these tools + math library are not / no longer free, so what's the deal? Microchip highly recommends the MPLAB XC16 Standard Compiler (SW006022-1) for new designs. $895 The MPLAB C Compiler for PIC24 MCUs and dsPIC DSCs is a fully ANSI compliant product with standard libraries for both architectures. It is highly optimizing and takes advantage of many architecture-specific features to provide efficient software code generation. If this is the case, I don't know if I really want to buy into this shit. There seems to be PIC16 support in LLVM since 2.4 Something to find out.. [1] http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010342 [2] http://zwizwa.be/staapl Entry: Dave on delay lines Date: Thu Nov 8 18:54:14 EST 2012 [1] http://www.youtube.com/watch?v=tQyX3F4ggM8 Entry: Cortex M4: ARM + DSP Date: Tue Nov 20 14:16:57 EST 2012 For the synth stuff, I'm thinking it's probably best to side-step weird 16bit architectures like dsPIC (no proper GCC / libc) and go for an ARM32bit that has an open source tool chain. Atmel SAM4 might be the best choice for now since I have some experience with the SAM7 (hoping the peripherals will be the same or similar). [1] http://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4 [2] http://www.atmel.com/products/microcontrollers/ARM/SAM4S.aspx Entry: Serial ports Date: Sat Nov 24 09:42:02 EST 2012 It's always been quite confusing to me. Really, I just care about the TTL level RX/TX ;) DTE/DCE Flow control: Null modem[1]: [1] http://en.wikipedia.org/wiki/File:D9_Null_Modem_Wiring.png Entry: Summon ARM Toolchain (SAT) Date: Wed Dec 5 13:14:00 EST 2012 So, after doing it by hand, it might be wise to switch to a more standard approach, i.e. SAT[1]. ImportError: No module named yaml apt-get install python-yaml [1] https://github.com/esden/summon-arm-toolchain Entry: Buffer cap Date: Mon Dec 10 15:32:19 EST 2012 Have a crappy UPS that glitches the router. Will a cap on the 9V work? 5 watts, 9V, 1 second. That's 500mA... or 500000uF Hmm... doesn't look like this will work. Pretty big cap. Even if it glitches for only .1 second it's still 50000uF. Box says 12V, but does it actually run off of a 9V battery? Let's wait until the plugs arrive since I'd have to cut it open.. Entry: Disassembling the Square Credit Card Reader Date: Tue Dec 11 12:30:47 EST 2012 [1] http://www.philipithomas.com/disassembling-square/ [2] http://www.google.com/patents/US7810729 Entry: FOSDEM 2013 Date: Sun Feb 3 13:45:16 CET 2013 Talk by Connor Abbot[1] about the Mali 200/400 pixel processor (PP) and geometry processor (GP). IIRC the PP is a fairly general purpose, deeply pipelined core, while the GP is a VLIW with a "feedback FIFO" architecture. The part last struck me as interesting: reading and writing ALU results from/to registers requires multi-port registers, which is expensive in silicon. A simple hardware trick is to feed back the output of the ALU to make it available on the next cycle in an array of FIFOs, which are cheaper than full-fledged readable/writable registers. [1] https://fosdem.org/2013/schedule/event/maliisa/ Entry: Lansing Inventors Network Date: Mon May 6 19:52:47 EDT 2013 [1] http://www.meetup.com/LansingInventorsNetwork/events/113501802/ Entry: Saleae Logic command line tools Date: Fri Jul 5 10:12:32 EDT 2013 Found 2 projects. saleae-logic-utils[1] seems to be just a proof of concept. It uses the Saleae Logic does have an SDK[3]. saleae-logic-libusb[2] actually works, but has an awkward design that makes it hard to change to streaming mode. [1] https://github.com/trygvis/saleae-logic-utils [2] https://github.com/keesj/saleae-logic-libusb Entry: EDA Date: Sat Jul 6 11:14:02 EDT 2013 http://en.wikipedia.org/wiki/KiCad http://en.wikipedia.org/wiki/DipTrace Entry: MSP430 LaunchPad Value Line Development kit Date: Sun Aug 18 01:16:28 EDT 2013 Debugger doesn't seem to be standard. [1] http://www.ti.com/tool/msp-exp430g2 [2] http://en.wikipedia.org/wiki/TI_MSP430#Debugging_interface Entry: What is an antenna Date: Mon Oct 14 20:58:09 EDT 2013 > What does something like an antenna do? How does it know what to do? > Is it mechanical or electrical or both or something else? Antennas exploit pure electro-magnetic (EM) phenomena which are captured by Maxwell's laws[1]. They have no moving parts (not mechanical). The way they operate is quite cool and antenna design is a deep black art. The creative act is to come up with original configurations of metal in space. I had it re-explained early this year by an old-time EE / HAM friend. I thought it would be interesting to try to explain to see if I get it. Here's an attempt: An antenna combines these two phenomena: (1) standing EM waves in a conductor (2) EM radiation in vacuum / air - Apply an alternating current (AC) of single frequency to a piece of metal. ( Note that most radio signals are "small band" which means for the sake of antennas they look like pure sine wave oscillations. Small band here means that the carrier frequency is much higher than the modulation applied to it == information content. ) - If the dimensions of the metal are tuned to the particular frequency of the alternating current, an oscillating standing wave pattern is created inside the metal[2]. ( Think of it as the EM waves being "trapped" inside the metal by the metal/air border: they reflect off of the edges of the metal. The standing waves are pretty much the same as for other physical vibrations, i.e. for mechanical tension/displacement vibrations in a bowed string, or air pressure vibrations a flute. The reason why this happens for an antenna is the same as for sound: electrical wave propagation speed is finite. ) - In vacuum (or air), any oscillating or otherwise accelerating electrical charge "radiates" a tiny bit of energy that propagates through space. ( One way to think of it is that an accelerating / oscillating electron changes energy, and that energy needs to go to / come from somewhere. This can only be done by emitting or absorbing photons. For a well-explained entertaining read on the theory of electrons and light, see [3].) - If you put a put a bunch of these oscillating charges next to each other (as in the manually crafted standing wave pattern in an antenna) you can "aim" the energy by using constructive/destructive interference: in some points in space contributions add up, in other they cancel out. You want to lay out the metal in such a way that when you apply an alternating current to the metal, most of the energy radiates away in the direction you desire. [1] http://en.wikipedia.org/wiki/Maxwell%27s_equations [2] http://en.wikipedia.org/wiki/Standing_wave [3] http://en.wikipedia.org/wiki/QED:_The_Strange_Theory_of_Light_and_Matter Entry: Mosfet voltage vs. current in active (saturation) mode Date: Fri Feb 7 18:58:06 CET 2014 Saturation or active mode is V_GS > V_T (on) V_DS > V_GS-V_T I_D ~ (V_GS - V_T)^2 I_D ~ V_ov ^ 2 V_ov = V_GS - V_T (overdrive) http://en.wikipedia.org/wiki/MOSFET Entry: Dependence on V_T Date: Fri Feb 7 19:52:59 CET 2014 IIRC, it's bad practice to have a circuit's operation depend on V_T, as this parameter is higly variable. E.g the 2N7002 has min/max of 0.8V to 3V, with a typical V_T of 2.1V at I_D = 1mA. What are typical tricks to do so? http://en.wikipedia.org/wiki/Threshold_voltage Entry: BJT & MOSFET, switching high-voltage load from 3.3V uC Date: Sat Feb 22 10:51:58 CET 2014 1. SWITCHING LOADS Breaks down into two cases, symmetric from the pov. of the load: - N) disconnect GND (load from V+) - P) disconnect V+ (load to GND) We want the transtor, either BJT or MOSFET, to be fully on/off. This requires an N-type for case N) and a P-type for case P), preserving symmetry of solution. When control voltage is the same as the output voltage, the switched behave as half of a CMOS inverter, with the other transistor replaced by the load. For BJT, simply add base resistor for current limiting, making sure it is driven to saturation. 2. WRONG POLARITY It's easy to set that the above works. So what goes wrong when we use an N type instead of a P type for a load to GND? An N type MOSFET won't be fully switched on. Since V_DS > V_GS - V_t, it is in saturation (current source) mode. For an N type BJT with a load to GND, there will always be at least 0.6V over the BE junction in the case the transistor is on, and if it's off it is operated in reverse cutoff (correct?) 3. LOW DRIVE VOLTAGE N/P symmetry gets broken when the control voltage is much smaller than the output voltage. Say V+ is 24V, typical for industrial control applications. This is where interrupting the ground lead becomes easer than interrupting the V+ lead. In the latter case, an extra inverter is necessary to generate the control voltage near V+. 4. BJT vs MOSFET * +BJT is easy to switch on (V_BE = 0.6V) * -MOSFET has unpredictable V_t * -BTJ introduces extra current in C->E path * -BTJ has I_B 5. GATE SOURCE BREAKDOWN The BS250P P-channel MOSFET has a G-S breakdown voltage of +- 20V. This means that in a 24V circuit load to GND switching situation, care needs to be taken to not pull the gate to GND, as this creates a -24V G-S voltage. To solve this, a 100k/100k divider network can be used at the gate input, switched to ground by a NPN. Entry: Working around +-20V gate-source breakdown Date: Sat Feb 22 14:41:50 CET 2014 Not so simple! I'm switching 24V, and there are plenty of occasions to get to |V_GS| > 20. http://books.google.be/books?id=bkOMDgwFA28C&pg=PA163&lpg=PA163&dq=mosfet+%22gate+source+breakdown%22&source=bl&ots=F3hiPJc0Sx&sig=_SEOMc1HAocCQ92jroJtvreHYDs&hl=en&sa=X&ei=16gIU77eDY-A7QapxYDwDQ&ved=0CCkQ6AEwAA#v=onepage&q=mosfet%20%22gate%20source%20breakdown%22&f=false Entry: Working around +-20V gate-source breakdown Date: Sat Feb 22 14:41:50 CET 2014 Not so simple! I'm switching 24V, and there are plenty of occasions to get to |V_GS| > 20. http://books.google.be/books?id=bkOMDgwFA28C&pg=PA163&lpg=PA163&dq=mosfet+%22gate+source+breakdown%22&source=bl&ots=F3hiPJc0Sx&sig=_SEOMc1HAocCQ92jroJtvreHYDs&hl=en&sa=X&ei=16gIU77eDY-A7QapxYDwDQ&ved=0CCkQ6AEwAA#v=onepage&q=mosfet%20%22gate%20source%20breakdown%22&f=false Entry: Loop-powered 4-20mA ICs Date: Sat Feb 22 17:02:22 CET 2014 http://www.analog.com/static/imported-files/data_sheets/AD421.pdf http://en.wikipedia.org/wiki/Highway_Addressable_Remote_Transducer_Protocol Entry: HART 4-20mA communication Date: Sat Feb 22 17:49:53 CET 2014 How can this be bi-directional? Entry: Simple load-modulated communication Date: Sat Feb 22 17:51:59 CET 2014 Single bus, multiple senders using load modulation. Can use any kind of RF modulation technique to share bus. Reception is tricky, but for unidirectional sensor nodes it might not be a problem. It's probably simpler to just use 1-Wire: http://en.wikipedia.org/wiki/1-Wire 3 or 5 V, 5k (1k long distance - 300m) Entry: Rail splitter Date: Fri Apr 25 19:22:18 EDT 2014 [1] http://www.ti.com/product/tle2426 Entry: LM324N -> swings to 0V Date: Fri Apr 25 19:41:45 EDT 2014 UNIQUE FEATURES In the linear mode, the input common-mode voltage range includes ground and the output voltage can also swing to ground, even though operated from only a single power supply voltage. [1] http://pdf.datasheetcatalog.com/datasheet/philips/LM324N.pdf Entry: MOSFETs in the box Date: Fri Apr 25 21:02:25 EDT 2014 I do have a couple of 2N7000 but these might have threashold voltages too close to 3V to be useful in 3V/3.3V application. I also found a IRF740 Entry: I want a digitally programmable voltage and current source Date: Mon Apr 28 16:09:51 EDT 2014 Basically, a voltage source is just a DAC. A current source is a DAC + opamp + transistor. Current source needs not be very high, so simple NPN should be good, otherwise use FET. What uC has a usable DAC? You know, this is a nice app for Staapl. Using a digital feedback loop, pwm can be used to drive the current sources. Entry: PWM for current setpoints? Date: Mon Apr 28 16:31:40 EDT 2014 Question: if freq > 20kHz, will there be any audible artifacts? Yes, it is possible for modulation and non-linearities to shift frequencies. Entry: ELM327 Date: Thu May 1 19:41:08 EDT 2014 ATL1 # linefeed on ATRV # voltage >01 01 41 01 00 04 00 00 41 01 81 07 65 00 >03 43 04 56 00 00 00 00 trouble code 0456 Entry: edge ringing Date: Sun May 4 17:52:30 EDT 2014 Ringing / overshoot on scope display for digital signals is probably about: - inductance of the ground lead - sharp edges to drive the resonnance Entry: ds1052e -> ds1102E Date: Mon May 5 19:43:06 EDT 2014 http://www.eevblog.com/forum/blog/changing-the-rigol-ds1052e-to-ds1102e-using-usb-the-dummy-guide/ Entry: Car again Date: Mon May 5 22:44:21 EDT 2014 picocom --baud 38400 /dev/ttyUSB0 >ATL1 >ATRV 12.6V >01 01 41 01 00 04 00 00 41 01 81 07 65 00 >03 43 04 56 00 00 00 00 EDIT: Same again, then I erased the code and put on a new gas cap (5/16). For now (5/24) it seems fine. >04 44 44 Entry: FPGA work Date: Wed May 7 13:22:30 EDT 2014 Some things to think about: - Openbench: PIC + Xylinx Spartan FPGA - Logic16: FX2 + Xylinx Spartan FPGA - Altera Cyclone IV coming soon in the mail Entry: Altera USB Blaster / USB Blaster II Date: Thu May 8 11:43:46 EDT 2014 See [2] - USB Blaster (terasIC) based on FTDI + Altera CPLD - USB Blaster II based on FX2 + Altera CPLD Then there are cheap $10 clones that have an FX2 but not the CPLD? http://www.eevblog.com/forum/microcontrollers/altera-usb-programmer/ http://www.ebay.com/itm/FT245RL-CPLD-High-speed-Solutions-USB-Blaster-Programmer-Altera-FPGA-Debugger-/331052143708 http://openocd.sourceforge.net/doc/doxygen/html/usb__blaster_8c_source.html http://www.edaboard.com/attachments/8358d1112601047-nios2_evaluation_1c12_board_schematic_131.pdf Entry: Low offset opamp replacement for LM324-N Date: Thu May 8 13:50:30 EDT 2014 LM324-N is cheap, works on a large voltage range, and can take in/out to 0V. However it has 2mV offset which is too much for precision amplification. A replacement can be LT1014[1]. Around $5-6 available in DIP[2]. Related: nulling LM324 offset voltages[3]. That refers to the TC914 chopper which seems obsolete. And a related thread at the eevblog forum[4]. Linear might be useful for their liberal sample policy and good website[5]. [1] http://www.linear.com/product/LT1014 [2] http://www.digikey.com/product-detail/en/LT1014CN/296-14616-5-ND/555846 [3] http://www.datasheetarchive.com/LM324%20nulling%20offset%20voltages-datasheet.html [4] http://www.eevblog.com/forum/projects/lm-324-upgrade/ [5] http://www.linear.com/parametric/Operational_Amplifiers_%28Op_Amps%29#!1076_yes!1030_|4!1004_%3E=24!1006_%3C=.2!gbw_!vsmax_24!ssupply_ssupply!sr_!ismax_!quad_quad!vos_.2!enoise_!vosdrift_!lfnoise_!ibias_!inoise_ Entry: Becquerel = decays / s Date: Thu May 8 17:39:26 EDT 2014 1 Bq = 27 pCi 6.7 picocurie = 0.2479 becquerel Entry: A function generator Date: Fri May 9 11:22:01 EDT 2014 I need a function generator for V, I_source, I_sink. V is just a DAC (+ buffer). Entry: 32kByte SRAM playback Date: Sat May 10 17:38:54 EDT 2014 23A256/23K256 can play back in sequential mode if you keep feeding it clock pulses, wrapping from 0x7FFF -> 0x0000. Max clock is 20MHz, which is 76Hz for full buffer playback AND record. Maybe something nice can be done by using two of these in ping-pong? Entry: Zeners Date: Sun May 11 17:29:08 EDT 2014 Have quite soft knees. Never knew that. Seing them all over the place in applications where a soft knee makes no sense.. Probably a good idea to get a feel for these before using them. I ordered a bunch. Then the idea is to use a component tester like this[1] to plot a curve. [1] http://www.youtube.com/watch?v=Gwo3pEH7hUE [2] http://sound.westhost.com/appnotes/an008.htm Entry: Schmitt trigger sawtooth Date: Sun May 11 19:12:06 EDT 2014 Interesting is the use of diodes to switch the current sources. [1] https://www.youtube.com/watch?v=ibnz5UjQ4u0 Entry: dsPIC interrupt magic Date: Mon May 12 15:04:21 EDT 2014 In p33FJ128GP804.gld the interrupt table __IVT_BASE at 0x4 is defined as a couple of conditional statements, one for each interrupt. If a particular symbol is not defined, the default interrupt will be used, eg: LONG( DEFINED(__T1Interrupt) ? ABSOLUTE(__T1Interrupt) : ABSOLUTE(__DefaultInterrupt)); Entry: Square wave output noise Date: Tue May 13 10:18:22 EDT 2014 What about powering a CD4049 CMOS hex inverter from a separate decoupled power supply? This wouls also allow differential outputs to be constructed easily without having to generate them in the PIC. Care needs to be taken to properly decouple if more than one signal is to be presented that is not always on. Maybe it's good to use 3 channels? Entry: Diode reference + non-inverting summing amp Date: Wed May 14 00:54:50 EDT 2014 Instead of lifting up the whole DAC, it might be simpler to add an offset to the signal after conversion using a non-inverting summing amp. The offset to add is about twice the max range, so a 2R / 1R ratio could do it. It's definitely a lot less finicky than lifting the ground. A nice thing about this is that the reference voltage is a diode drop, so no hassle with resistors. The range will be +- ok by itself so no need to worry about huge current differences. Entry: Non-inverting summing amp Date: Wed May 14 01:15:19 EDT 2014 Type: tex A non-inverting summing amp is essentially an averaging operation (tie N sources using resistors into a star) followed by a buffer or typically non-inverting gain stage to compensate for the lost gain due to averaging. The interesting behavior is in the weighted average following from Kirchhoff's current law $$\sum_i {V_i - V \over R_i} = 0\text{ or }\sum_i G_i (V_i - V).$$ The weighing happens according to \emph{conductance} $$V = {\sum_i G_i V_i \over \sum_i G_i}.$$ Also used with positive feedback in the classical Schmitt--trigger circuit: $\frac{1}{3} V_{+} + \frac{1}{3} V_- + \frac{1}{3} V_{c}$ with $V_c$ the comparator output. Entry: Component tester Date: Fri May 16 15:55:42 EDT 2014 Using the octopus approach[1], but without a transformer. Sine waves seem indeed a good idea wrt. reactive compones as opposed to saw tooth waves. So how to generate the negative voltage from a battery? Pita.. Maybe transformer is a better option. Entry: Digital decade box Date: Fri May 16 16:13:30 EDT 2014 If done digital, better to make a binary one with an analog switch or some optocouplers. Or make a ballpark switch using the standard range. Nice manual one here[1]. [1] http://www.digitalunderpants.com/diy-resistor-substitution-decade-box/ Entry: PIC comparator / capture-compare Date: Sat May 17 11:57:36 EDT 2014 In 18F4550[1] data sheet these are relevant: 15.0 Capture/Compare/PWM (CCP) 16.0 Enhanced Capture/Compare/PWM (ECCP) 22.0 Comparator Module Two comparators tied to RA0-RA5 or voltage reference. Outputs available at pin level. Interrupts happen when there is a change in ouput value. 23.0 Comparator Voltage Reference Module 16-tap resistor ladder network derived from V_REF+/V_DD and V_REF-/GND (8-16-8 or 8-16 divider). The voltage can be sent out to RA2 to be used as a 3-bit DAC. [1] http://ww1.microchip.com/downloads/en/DeviceDoc/39632e.pdf Entry: Audio scale units Date: Sat May 17 14:01:03 EDT 2014 Following chuck moore's advice: pick good units! Trying to get a good idea of units for audio synth applications. Order of magnitude: 20mA, 20kHz, 2.2mV (sawtooth from current through cap). These seems proper units: mA kHz V uF kOhm Derived from main equation: C = I / f V -> uF = mA / kHz V (/ 0.001 (* 1000 1)) = 10E-6 So caps are in the nF-uF range, with impedances of: Ohm from Hz, F kOhm from kHz, uF 20kHz -> 17 Ohm (/ 1.0 (* 6.28 20000 0.00000045)) (/ 1.0 (* 6.28 20 0.45)) 20hZ -> 18 kOhm (/ 1.0 (* 6.28 20 0.00000045)) (/ 1.0 (* 6.28 0.020 0.45)) So typically nA and pF range parasitic values can be ignored. Those are important mostly for MHz applications, not kHz. EDIT: Let's try that out on a diode ladder computation: f = 1 / 2 pi R C R = V_T / I => f = I / 2 pi V_T C mA mV uF kHz (/ 1 (* 6.28 25 0.33)) 0.019 Entry: BJT: switching or amplifier? Date: Sat May 17 14:43:06 EDT 2014 What's the difference between BJTs designed for switching applications vs. amplifier applications? Some differences: - Max current - Noise - Different distribution of capacitances Datasheets don't tell me much. How to get an answer to this? NPN BC549 switching + amplifier 2N3904 general purpose amplifier MOSFET 2N7000 Is the only one I found mentioning pulsed currents of 2A (400mA sustained. Suggested as a gate driver = charging/discharging a capacitor. Entry: Capture / Compare Date: Sat May 17 19:31:47 EDT 2014 CAPTURE[1]: Record time stamp of an input event. COMPARE[2]: Trigger output at specific time. [1] http://en.wikipedia.org/wiki/Input_capture [2] http://en.wikipedia.org/wiki/Output_compare Entry: 2N7000 PMOS equivalent? Date: Sat May 17 20:58:55 EDT 2014 See [1]. TP0610 SOT-23 ZVP3306 TH, $1 ZVP2106A TH, $1 BSS84 SOT-23 DMG1013 SOT-23, $0.03 (DMG1012 N) Time to figure out how to use SOT-23 packages on breadboard. I ordered some adapters[2], but maybe also possible on perf board[3]. [1] https://groups.google.com/forum/#!topic/sci.electronics.design/og2iI9I1IzM [2] http://www.ebay.com/itm/331201529579 [3] http://www.theengineertutor.com/convert-very-small-sot23-5-package-to-through-hole/ Entry: Capacitance Date: Sun May 18 21:57:18 EDT 2014 The speed of the 2N7000 with 10k gate resistor surprised me (3.5uS charge discharge time for a 45nF cap on 3.3V). ( EDIT: this was probably due to a 22k pull down resistor I missed, setting V_GS too low. ) What's the gate capacitance? 20pF typical, 50pF max. t_RC = (* 10e3 20e-12) 0.2uS so that's not it. Maybe cap of breadboard[1]? 10pF rule-of-thumb according to Dave, rule of thumb don't do >1MHz on breadboard. After measuring it's 2.5pF between strips and 20pF on the power strips. [1] http://www.eevblog.com/2014/01/15/eevblog-568-solderless-breadboard-capacitance/ Entry: R/2R ladder DAC for PIC18 function generator Date: Mon May 19 00:43:58 EDT 2014 I wonder, how fast can data be sent over a PIC18 port? For a function generator, a DIY R/2R ladder might be good enough. If data is from ram and we have dedicated operation, probably 2 cycles per sample. A sawtooth can be done faster by just incrementing the port register. That would be a nice hack for a fixed frequency function generator, but then a counter would be good enough. Maybe this can be used as a shepard tone generator? Entry: Switched capacitor variable resistor? Date: Mon May 19 11:02:40 EDT 2014 Is it possible to make a variable resistor using a switched capacitor design where the frequency is varied[1]? For practical use in audio apps the low end needs to be > 20kHz. Say we can vary 20kHz to 20MHz, that's 1000x which spans the useful frequency range. Of course the idea is not new[2]. Now the question is: can frequency be changed accurately enough? Is there a way to construct base frequency + frequency difference using multiplication? At low frequencies, uC resolution is high enough. At high freqs it's not. The thing is that the EIDAC circuit can probably be used for that. Wide frequency range, with errors proportional to frequency, and a digital control loop that could in principle reach zero average error. [1] http://en.wikipedia.org/wiki/Switched_capacitor#The_switched_capacitor_resistor [2] http://en.wikipedia.org/wiki/Switched_capacitor#The_Parasitic_Sensitive_Integrator Entry: CPLD Date: Mon May 19 11:46:17 EDT 2014 So, if FPGA's are a mess, what would be a simple CPLD to start exploring? Something in DIP? Maybe ATF2500C? The question would be programming. Are specs available? I don't want to use your tools.. Or a 22V10[3]? I was thinking about these: ATF2500C-20PU CPLD 24MC 20NS 40DIP ATF750C-10PU CPLD 10MC 10NS 24PDIP ATF22LV10CQZ-30PU PLD 10MC 30NS 24DIP ATF22V10C-10PU PLD 10MC 10NS 24DIP ATF22V19C-7PX EE PLD 500GATE 5V 7NS 24DIP But need to check the DS first to make sure they are multiple-times programmable. Only last one says EE? [1] http://www.atmel.com/Images/doc0777.pdf [2] http://dangerousprototypes.com/2011/03/14/trivia-cpld-on-a-pdip/ [3] http://en.wikipedia.org/wiki/Programmable_Array_Logic [4] http://www.atmel.com/products/other/spld-cpld/default.aspx Entry: Bitbang send-only 10M ethernet Date: Mon May 19 12:53:23 EDT 2014 [1] http://www.epanorama.net/newepa/2011/10/30/bitbang-ethernet/ Entry: Breadboard mixer Date: Tue May 20 18:44:01 EDT 2014 I need something that connects to TRS for long wire transport and has a volume knob. 4 channels might be enough. I.e. a good channel strip board. Entry: Sallen Key Date: Fri May 23 11:47:52 EDT 2014 I've always been intrigued by the Sallen-Key[1] (SK) topology. One of those strange bootstrappy circuits. After learning the Korg filter is a SK with resistors replaced by diodes / reverse transistors[2] I've been even more intrigued. Who comes up with that stuff? At first glance it seems counter-intuitive, so I'm more interested in how one would invent such a circuit than to just calculate the transfer function, which is straightforward. [1] http://en.wikipedia.org/wiki/Sallen%E2%80%93Key_topology [2] http://www.timstinchcombe.co.uk/index.php?pge=korg Entry: uCurrent precision opamp Date: Sat May 24 00:20:55 EDT 2014 MAX4239 [1] http://www.eevblog.com/files/uCurrentArticle.pdf Entry: 2N3904 thermal resistance Date: Sun May 25 18:39:33 EDT 2014 1mA at 670mV is 0.670mW. Thermal Resistance, Junction to Ambient is 200C/W. So temperature gradient is (* 200 0.00067) 0.134C Entry: 4049UBE current mirror Date: Sun May 25 23:08:04 EDT 2014 Not connecting V+ or V- gives a set of 6 thermally coupled nMOS or pMOS transistors with common drain / source. Should work as a current mirror. Though I'm not sure if MOS current filters work over as wide a range as BJTs. Entry: Darlington exp converter Date: Mon May 26 00:50:30 EDT 2014 Since monolithic darlington arrays are easier to find as compared to single NPN arrays, it might be interesting to find out if they can be used as an (approximate?) exp converter as well. The ULN2001[2] might work, though I'm not sure what the point is of the resistors nor if they would interfere.. According to H&H the resistors are there to turn off the transistors faster. [1] http://octopart.com/partsearch#!?q=darlington%20array [2] http://datasheet.octopart.com/ULN2003D1013TR-STMicroelectronics-datasheet-165970.pdf Entry: Headroom for LM324N / LM13700 / 2N7000 Date: Mon May 26 10:37:54 EDT 2014 LM324N needs about 2V at V+. This space can be used to also place some other control hardware for e.g. linearized FET resistors referenced to ground. For the LM324N with 5V supply we have about 3V headroom, placing the midpoint at 1.5V. Many USB usb don't make it to 5V really. What about setting midpoint at 1V, which gives a +-1V swing. Should be enough. Is there any limitation on output voltage for the LM13700? Output stage are a diode drop + a saturation limit on both sides, say 3 diode drops, 4 in total is (* 0.63 4) 2.5V. This could work but really needs the signal ground to be in the middle of the larger supply node. Probably will end up with multiple virtual grounds. The 2N7000 MOSFET needs about 3V. Designing the circuit around large R_DS makes it possible to stick close to that threshold. Entry: Linearized FET resistor Date: Mon May 26 10:47:09 EDT 2014 I was reading H&H yesterday and ran into the linearized FET resistor circuit[1]. Because of large V_th variation, this will only work in a feedback circuit. [1] http://graffiti.virgin.net/ljmayes.mal/comp/vcr.htm Entry: 2mV V_BE mismatch Date: Mon May 26 20:49:54 EDT 2014 Where does that figure come from? It is in the order of a 10% current mismatch when used directly in a current mirror. (exp (/ 2.0 26.0)) -> 8% [1] http://electronics.stackexchange.com/questions/96915/typical-transistor-mismatch-for-2n3904-2n3906 Entry: Typical C / I for diode filters Date: Tue May 27 17:05:43 EDT 2014 It seems that dynamic resistance is quite low for the current range 1mA - 1uA which seems most useful for this type of circuit. (EDIT: this was a bad intuition. I've seen these circuits with LEDs that light up[1], so at least there should current in the mA range. Typical range of C in circuits is around 20nF.) Diode resistance is V_T / I with V_T approximatly 25mV, this gives R: 25 Ohm @ 1mA 25 kOhm @ 1uA Actually, this maps fairly well into the nF capacitor values. e.g. the "audio units" mA kHz V uF kOhm f = 1 / 2 pi R C R = V_T / I => f = I / 2 pi V_T C Here are some ratios between I and C that would work to get the high point at audio range. Low point will just be 1000x less. Here V_Tf is the "thermal frequency voltage" 2 pi V_T corresponding to V_T=0.255 f = I / V_Tf C V_Tf is about 0.16V or 6/V mA V uF kHz (/ 1 (* 0.16 0.330)) => 19 (/ 1 (* 0.16 0.220)) => 28 (/ 0.5 (* 0.16 0.100)) => 31 (/ 0.1 (* 0.16 0.033)) => 19 (/ 0.1 (* 0.16 0.022)) => 28 (/ 0.05 (* 0.16 0.010)) => 31 [1] https://www.youtube.com/watch?v=3gCy_LfeaFs Entry: Cheap 5V rail-to-rail opamp available in DIP Date: Fri May 30 23:58:41 EDT 2014 The LM324N is good enough for most things, but I'd like to find a good 5V rail2rail for when I need it. LMV324L[1], similar in price to LM324N. Available in DIP, Microchip seems to be the cheapest. These have a 550kHz GBW, 5mV offset, 35mV from rails[2] MCP6241-E/P MCP6242-E/P MCP6244-E/P MCP6004-I/P-ND similar with 1MHz GBW[3]. Next up is TI TL972IPE4 TL974IN (<$1), low noise, low distortion, gbw 12MHz[4]. Looks like a nice one. The also mentioned here[6] is the TLV2371[5] and LM6142[7]. Mentioned here[8] is the TLV2774[9]. [1] http://www.st.com/web/en/resource/technical/document/datasheet/DM00052423.pdf [2] http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP6244 [3] http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP6004 [4] http://www.ti.com/product/tl974 [5] http://www.ti.com/product/tlv2371 [6] http://forum.arduino.cc/index.php/topic,86146.0.html [7] http://www.ti.com/product/lm6142 [8] http://www.swarthmore.edu/NatSci/echeeve1/Ref/SingleSupply/SingleSupply.html [9] http://www.ti.com/product/tlv2774 Entry: Reverse saturation Date: Sat May 31 01:58:12 EDT 2014 I'd like to derive this again[1]: an explanation for the use of a transistor in reverse saturation to make a current controlled resistor. I'm not sure I really get why it has to be reverse and not forward. Is this just to make the resistance value say 50x larger? To understand, look at the point where reverse and forward beta are compared: that's where the approximations will differ. Though following that through gives a similar expression. Check again... [1] http://www.timstinchcombe.co.uk/synth/MS20_study.pdf Entry: MAX4167 Date: Sat May 31 12:36:55 EDT 2014 Some Maxim rail to rail opamp samples left from a past project: 4x MAX4167[1] High-Output-Drive, Precision, Low-Power, Single-Supply, Rail-to-Rail I/O Op Amps with Shutdown 5x MAX494[2] Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op Amps [1] http://www.maximintegrated.com/en/products/analog/video-products/amplifiers/MAX4167.html [2] http://www.maximintegrated.com/en/products/analog/video-products/amplifiers/MAX494.html Entry: BNC-T to two scopes: don't use 10x probes Date: Sun Jun 8 15:46:57 EDT 2014 I have both a cheap digital Rigol DS1052E and an old analog scope hooked up to the same probes, probing high impedance points in an analog synth circuit. Obvious in retrospect, but when you do this, don't use the probe in 10x mode! It will divide against 500k instead of 1M and so reduce the gain to .5/(9+0.5) instead of 1/10, and seemingly distort the waveform to boot. Entry: "Lossless" is ambiguous: Transfer Function vs. Impedance Date: Fri Jun 13 08:57:23 EDT 2014 There is a big difference between a lossless transfer function and a lossless electronic circuit as the "loss" refers to two different things: signal level vs. signal energy. A lossless transfer function needs to have a flat frequency response, i.e. it's an allpass filter a.k.a. phase shifter. A lossless circuit takes the form of a frequency dependent impedance, e.g. an LC low-pass filter between power switcher and load in a class D amplifier. What is confusing in the latter is that a lossless circuit is often used in combination with an ohmic load to create a freqency-dependent signal transfer function. There is obviously "loss" in the form of dissipation in the load, however there is no loss in the L and C apart from parasitics. Entry: Long cable lengths? Date: Fri Jun 13 12:33:15 EDT 2014 I need a simple way to buffer a signal and carry it to a scope on the other side of the bench. I'm not too interested in details so things like slew rate distortion and offset due to op amp buffering are not a problem. Entry: Pot -> resistor Date: Sun Jun 15 00:53:34 EDT 2014 How bad does non-linearity get when we feed an inverting summing amp from a voltage divider / pot, and the impedances are similar? Entry: Check engine Date: Sat Jun 21 17:07:27 EDT 2014 Terminal ready OKL1 >ATRV 12.3V >01 01 41 01 00 04 00 00 41 01 82 07 65 00 >03 43 04 56 02 34 00 00 0456 EVAP Control System Leak Detected Very Small Leak 0234 Engine Over Boost Condition Entry: Microchip XC16 dspic33FJ128GP804 code entry point Date: Wed Jun 25 16:19:48 EDT 2014 Code and data addresses are defined in the linker script. Look for p33FJ128GP804.gld and modify. Entry: Function generator Date: Thu Jun 26 10:48:06 EDT 2014 Need a function generator for current project. Entry: PIC32 in DIP28 ? Date: Mon Jul 7 03:46:20 EDT 2014 Now that's a nice surprise. See comments here[1]. The PIC32MX250 is mentioned here[2]. To bad about the tool chain business though. [1] http://hackaday.com/2013/10/15/breadboarding-with-a-arm-microcontroller/ [2] http://hertaville.com/2012/12/17/the-case-for-the-pic32/ Entry: Check engine again Date: Tue Jul 22 11:53:09 EDT 2014 picocom --baud 38400 /dev/ttyUSB0 >ATL1 >ATRV 12.6V >01 01 41 01 00 04 00 00 41 01 81 07 65 00 >03 43 04 97 00 00 00 00 497 Evaporative Emission (EVAP) System Low Purge Flow http://www.matthewsvolvosite.com/forums/viewtopic.php?f=9&t=62069 (8/7 checked again: same, erased with 04) Entry: BeagleBone PRU Date: Thu Jul 24 00:08:47 EDT 2014 Just found out via Hackaday [2][3] that the BeagleBone Black[4] has two unused microcontrollers with shared memory into the Cortex A8. Used in BeagleLogic[15]. Called PRU for Programmable Realtime Unit. TI whitepaper[5]. TI Wiki[8]. More info at BeagleBoard site[6]. Main soc is called Sitara[7]. PRU seems to be small custom processor. There's a GCC[9]. Someo more info [10][11][12][13]. From [14]: - no multiply - no stack - bit manipulation - memory and io access - power management of main cpu [1] http://elinux.org/ECE497_BeagleBone_PRU [2] http://hackaday.com/2014/06/22/an-introduction-to-the-beaglebone-pru/ [3] http://hackaday.com/2014/07/22/talking-beagleboard-with-jason-kridner/#more-127242 [4] http://beagleboard.org/black [5] http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=spry136&fileType=pdf [6] http://elinux.org/BeagleBone_PRU_Notes [7] http://www.ti.com/lit/pdf/spruh73 [8] http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit?keyMatch=Programmable%20Real-time&tisearch=Search-EN [9] http://elinux.org/Ti_AM33XX_PRUSSv2#GCC [10] http://www.element14.com/community/community/designcenter/single-board-computers/next-gen_beaglebone//blog/2013/05/22/bbb--working-with-the-pru-icssprussv2 [11] http://www.embeddedrelated.com/showarticle/586.php [12] http://www.embeddedrelated.com/showarticle/603.php [13] http://embedded.fm/episodes/2014/7/22/60-fun-things-you-can-make-out-of-beagles [14] https://www.youtube.com/watch?v=8SQlh1CPwsA [15] http://www.theembeddedkitchen.net/tag/logic-analyzer/ Entry: gas cap Date: Fri Aug 8 15:04:47 EDT 2014 picocom --baud 38400 /dev/ttyUSB0 >ATL1 >ATRV 12.7V >01 01 41 01 81 07 65 00 >03 43 04 56 00 00 00 00 >04 44 44 > Entry: evap Date: Wed Aug 13 12:35:22 EDT 2014 >03 43 04 97 00 00 00 00 Entry: EtherCat Date: Sat Sep 20 21:54:54 CEST 2014 The thing with EtherCat is that the setup process is relatively complicated wrt. running the control loop when it is finally set up. Why not write the setup in a scripting language like Python to then pass control to a RT core in C running e.g. on RTLinux or even on a RTOS / state machine ARM. With BeagleBones selling at $45 these days, it seems that from now on it makes a lot of sense to split applications into a "compiler" part running on a Linux host, and a core statemachine part running on the bare micro. Entry: Beaglebone PRUs Date: Mon Oct 6 02:42:07 CEST 2014 [1] https://www.youtube.com/watch?v=ZNz45v9Uesg [2] https://www.youtube.com/watch?v=y8-gwthzf-c Entry: viewing gerbers Date: Thu Nov 20 11:06:16 EST 2014 gerbview *.G* gerbv *.G* GBL: bottom layer GBS: bottom soldermask GD1: drill guide GG1: drill guide (top to mid 1) GTL: top layer GTO: top silk screen GTP: top paste GTS: top solder G1: ? G2: ? GBO: bottom overlay GBP: bottom paste [1] http://de.wikipedia.org/wiki/Gerber-Format Entry: check engine Date: Fri Dec 5 10:47:41 EST 2014 picocom --baud 38400 /dev/ttyUSB0 >ATL1 >ATRV 11.5V >01 01 41 01 00 04 00 00 41 01 81 07 65 00 >03 43 04 97 00 00 00 00 497 Evaporative Emission (EVAP) System Low Purge Flow http://www.matthewsvolvosite.com/forums/viewtopic.php?f=9&t=62069 >04 44 44 > Entry: USB extender over CAT5 Date: Wed Dec 17 23:23:59 EST 2014 Only for 12MBit http://www.monoprice.com/Product?c_id=103&cp_id=10303&cs_id=1030313&p_id=6042&seq=1&format=2 Entry: TP-LINK TL-PA2010KIT / QCA6410 Date: Sun Dec 21 14:59:19 EST 2014 QCA6410 AL3C ST1P7.1B T349 TAIWAN On the ethernet side, these devices operate at the data-link layer (Ethernet, not IP). See [1] (build it, then see docbook/index.html) zoo:/home/tom/git/open-plc-utils/plc# ./int6k -i br0 -r The Actiontec PWR200K01 also has a QCA6410. Tool can reset the device: ./int6k -i br0 -R So looks like link monitoring + reset can be done in software. [1] https://github.com/qca/open-plc-utils/tree/master/ether Entry: elua low memory patches Date: Tue Dec 23 21:12:13 EST 2014 [1] http://www.eluaproject.net/doc/v0.9/en_arch_ltr.html Entry: STM32F103 futurlec Date: Tue Dec 23 21:17:14 EST 2014 [1] http://www.futurlec.com/ET-STM32_Stamp.shtml Entry: Kicad <-> Altium Date: Sun Dec 28 21:08:28 EST 2014 Apparently there are scripts growing in the Novena Laptop community to convert Altium schematics and board layoout to Kicad. Entry: Cisco routers Date: Mon Dec 29 17:33:30 EST 2014 I've got a box of cisco routers. Maybe these can be repurposed to ethernet boxes, possibly driving PIC chips ENC28J60[2]. Trouble is power though[1]. And these days it seems that just going for something like a Beaglebone is probably better. I keep coming back to the topology which has Ethernet (with PoE) running to a Linux box, then 5m fanout for USB microcontrollers. It seems really not worth the trouble to have the power overhead of ethernet combined with a tiny uC. If BBB is $45, in a couple of years this is going to be nothing. [1] http://electronics.stackexchange.com/questions/52349/why-is-ethernet-so-power-hungry [2] http://www.ebay.com/itm/like/201244700646?lpid=82&chn=ps Entry: am230x temperature sensor sigrok decoder Date: Tue Dec 30 22:56:11 EST 2014 http://sigrok.org/wiki/Protocol_decoder:Am230x Entry: Mounting pcbs without holes Date: Mon Jan 12 17:51:03 EST 2015 This pops up a lot: how to mount a pcb to a (wooden) carrier if it doesn't have any holes? I'm looking for (plastic) X-shaped stubs with a hole in the middle, and a ridge to hold the board. Just ridges would already be ok. Alternatively, use a piece of pcb and some wooden or plastic standoffs? I do have this moldable plastic so maybe that's a way to go. Entry: switch readout Date: Sun Jan 18 23:53:55 EST 2015 Had a look at scope's front panel readout. Each switch / rotary encoder half has a diode in series. Readout seems to be time-multiplexed. Bus is a resistive pullup. How is this supposed to work? Can't figure it out atm. Here's[1] an explanation. [1] http://www.openmusiclabs.com/learning/digital/input-matrix-scanning/ Entry: dsPIC PLL Date: Wed Feb 11 19:08:58 EST 2015 Can the on-chip PLL be used to synthesize an external clock? I'm trying to solve the following problem: - Generate a 6MHz signal from a signal in the 60kHz range, +- 0.5% - The reason for the 60kHz is that I want to use a uC timer to drive the PLL. Running at 72MHz a 1000-count gives me about 0.1% of precision. So I need about a 64x or 128x PLL. Probably more hassle than getting an off-the-shelf PLL. Entry: Pot resolution - dithering Date: Sun Feb 22 19:47:00 EST 2015 How to change the resolution of a pot to dramatic levels? I'm talking about beyond the resolution of the adc, and over time spans of say a second. Add a little white noise that crosses the 1 bit threshold. How to do that? Maybe just using hum or other non-white noise present in the system is already enough as long as the _sampling_ is done randomly to avoid creating correlations (beating). Entry: MOSI and MISO Date: Tue Mar 3 18:22:12 EST 2015 I always wondered why SPI pins are MOSI / MISO and not RX / TX. E.g. switch master to slave swiches the function of a pin between input and output. Entry: PLL stability Date: Fri Mar 6 16:08:15 EST 2015 How to prevent a PLL from oscillating? It seems that stabilty is mostly due to linear delay inherent in phase measurement of digital signals. This delay acts as a comb filter, so it seems the loop lowpass filter needs to suppress the second and subsequent lobes in that comb. Entry: Simple synths: monotron mods Date: Sat Mar 21 01:51:39 EDT 2015 - Add comparator to create square w. PWM - D FFs for sub-osc. (actually 4040 binary counter) [1] https://www.youtube.com/watch?v=Ntnd1CmJAN0 Entry: Flip-Flops Date: Tue Mar 24 23:09:22 EDT 2015 Time to re-acquaint with flip-flops. Entry: check engine Date: Wed Apr 1 10:23:55 EDT 2015 picocom --baud 38400 /dev/ttyUSB0 ATRV >11.5V >01 01 41 01 81 07 65 21 >03 43 04 97 00 00 00 00 evap again Entry: Rigol DS1054Z decode function Date: Thu Apr 9 12:15:50 EDT 2015 https://www.youtube.com/watch?v=SarsWOCMvjg http://hackaday.com/2014/11/12/how-to-get-50-more-zed-from-your-rigol-ds1054z/ http://gotroot.ca/rigol/riglol-103d/ As usual, hard to find complete non-contradicting information. google riglol DSER (no 500uV option). Apparently buggy: http://www.eevblog.com/forum/testgear/ds1000z-serie-unlocking/ http://www.eevblog.com/forum/testgear/sniffing-the-rigol%27s-internal-i2c-bus/msg432125/#msg432125 http://www.eevblog.com/forum/testgear/is-ds1054z-with-firmware-00-04-02-sp3-hackable/ Entry: 433.92 MHz Date: Sun May 10 15:53:05 CEST 2015 Protocols? See [4]: OOK_PWM_D OOK_PWM_P OOK_MANCHESTER OOK_PWM_RAW [1] http://www.eevblog.com/forum/beginners/433-92-mhz-receiver/15/ [2] http://www.instructables.com/id/RF-315433-MHz-Transmitter-receiver-Module-and-Ardu/ [3] http://dangerousprototypes.com/2014/06/25/analysing-433-mhz-transmitters-with-rtl-sdr/ [4] https://github.com/merbanan/rtl_433 [5] http://www.rfxcom.com/epages/78165469.sf/nl_NL/?ObjectPath=/Shops/78165469/Products/14103 [6] https://electronics.stackexchange.com/questions/38318/how-rf-443-92-mhz-works Entry: Check engine jetta Date: Mon May 18 00:29:21 CEST 2015 picocom --baud 38400 /dev/ttyUSB0 >ATL1 >ATRV 12.2V >01 01 SEARCHING... 41 01 00 04 00 00 41 01 81 07 E5 00 >03 43 00 43 01 24 04 Entry: GLB Date: Fri May 22 15:30:18 CEST 2015 Basic idea: interrupt a loop by placing a low-value resistor in the loop path (e.g. 5 Ohm) separating internal and external grounds, then use a differential input/output to reference the external ground. It seems that the cause is *not* transformer coupling which is what I originally thought. From Appending C in [1] the way to explain it is: 1. power supply currents (operating and decoupling "spikes") are large. 2. relative to size of current, the power supply resistance is not negligible, creating ground levels that are not the same 3. generally, the impedance of a shield cable connecting two such grounds is large enough to not not pull the grounds to the same potential, i.e. a voltage drop is present. this signal is the audible noise. [1] http://www.ti.com/lit/an/sloa143/sloa143.pdf Entry: RS485 polarity numbering Date: Sat Sep 12 17:12:03 CEST 2015 This is very confusing. What works for me, using A/B naming convention from chip manufacturers: - A=D+ non-inverting / B=T- inverting - uC UART IDLE is logic HIGH, A > B. T+ > T- The RS485 names A/B opposite[1]. Thanks! [1] http://www.bb-elec.com/Learning-Center/All-White-Papers/Serial/%95-Polarities-for-Differential-Pair-Signals-%28RS-422.aspx?utm_source=redirect&utm_medium=SiteTransition&utm_content=bbeurope Entry: Phytec UART issue Date: Sat Sep 12 18:03:58 CEST 2015 http://phytec.com/wiki/index.php?title=PhyCORE-Vybrid_SCI2_Support&oldid=2902 Entry: temperature sensors Date: Fri Oct 9 18:31:41 EDT 2015 Protocol is PWM, so needs accurate timing to receive. Would like to run it on BeagleBoard xM, but it's probably best to use a uC instead. http://www.micropik.com/PDF/dht11.pdf Entry: Thermostat connector Date: Fri Oct 9 19:15:57 EDT 2015 B black wire O G Y W yellow wire - not used R \ RC / R and RC are bridged. 60Hz, 27V between B and Y. B is 24V "neutral" This is a 2-wire system from an old mercury thermostat. Connecting black and yellow gives about 0.1A current. https://wiki.xtronics.com/index.php/Thermostat_signals_and_wiring https://www.youtube.com/watch?v=CLBPsdATeZg Entry: Open firwmare wifi card Date: Sat Jan 16 18:38:08 EST 2016 https://wiki.debian.org/ath9k_htc/open_firmware https://www.youtube.com/watch?v=niu14NoLeQc http://www.ebay.com/itm/ALFA-AWUS036NHA-802-11n-Wireless-N-Wi-Fi-USB-Adapter-High-Speed-Atheros-AR9271-/380458349886?hash=item589515b53e:g:EcgAAMXQTZhR0E5n ALFA-AWUS036NHA-802-11n-Wireless-N-Wi-Fi-USB-Adapter-High-Speed-Atheros-AR9271 Entry: "standard" DC power jacks Date: Sat Jan 23 10:33:05 EST 2016 Ebay search for "panel mount power connector". Which one is it? - 5.5mm x 2.1mm -> measured OK - 5.5mm x 2.5mm Entry: crossing clock domains - metastability Date: Mon Feb 1 17:12:23 EST 2016 http://www.fpga4fun.com/CrossClockDomain.html Entry: Metastability / Synchronizer Date: Mon Feb 1 23:07:22 EST 2016 http://www.eetimes.com/author.asp?section_id=36&doc_id=1320153 Entry: VHDL Date: Tue Feb 2 22:16:32 EST 2016 architecture: - structure: instantiate components, map ports (schematics) - dataflow: . <= . . (signal propagation) - behavioral: based on sequential processes (abstracted from implementation) - rtl: .. Processes execute top to bottom, triggered by events in the sensitivity list. It is important not to confuse variables and signals, as described in [2]. [1] http://gmvhdl.com/VHDL.html [2] http://www.gmvhdl.com/signals.htm Entry: ghdl Date: Tue Feb 2 22:55:39 EST 2016 http://ghdl.free.fr/ http://vorboss.dl.sourceforge.net/project/ghdl-updates/Builds/ghdl-0.33/ghdl-0.33-x86_64-linux.tgz http://home.gna.org/ghdl/ghdl/A-full-adder.html Entry: vhdl vs verilog Date: Wed Feb 3 00:13:15 EST 2016 some interesting remarks and references[1]. [1] http://electronics.stackexchange.com/questions/16767/vhdl-or-verilog [2] http://insights.sigasi.com/opinion/jan/verilogs-major-flaw.html Entry: mydhl Date: Wed Feb 3 00:23:11 EST 2016 apt-get install python3-pip python3-setuptools pip3 install myhdl Synthesis: http://docs.myhdl.org/en/stable/manual/conversion.html#conv-subset Entry: VCD - Value Change Dump Date: Wed Feb 3 00:47:02 EST 2016 as used in GTKWAVE https://en.wikipedia.org/wiki/Value_change_dump Entry: FPGA muxes Date: Thu Feb 4 11:13:03 EST 2016 If FPGA vendors "sell wires", can muxes be optimized to interconnect? Entry: Metastability and Firmware Date: Sun Feb 7 10:35:59 EST 2016 http://www.ganssle.com/articles/MetastabilityandFirmware.htm Entry: TeX circuit drawing Date: Sun Feb 14 11:19:35 EST 2016 http://www.texample.net/tikz/examples/area/electrical-engineering/ Entry: Schematics are raw Date: Sun Feb 14 16:51:10 EST 2016 I didn't know this, but schematics files (gschem and ltspice) are just collections of lines (nets) and symbols. The connectivity is implicit: if lines meet at the same (exact!) point, they connect. http://wiki.geda-project.org/geda:file_format_spec Entry: Volka beats adapter Date: Thu Feb 18 17:36:38 EST 2016 Plug is not standard, 1.7mm http://music.cornwarning.com/2014/10/02/getting-a-good-korg-volcabeatskeysbass-ac-power-adapter/comment-page-1/ Entry: SPI Date: Sun Feb 21 02:20:07 EST 2016 Something I learned about SPI. The MISO pin on slave devices is switched to hi-Z when CS=1, so they can be wired together. Entry: volca Date: Sun Feb 28 03:17:59 EST 2016 http://www.generalimprovement.co.uk/Interview.htm Entry: EDIF Date: Sun Mar 13 17:48:00 EDT 2016 https://en.wikipedia.org/wiki/EDIF Entry: SDF - standard delay format Date: Sun Mar 13 17:49:42 EDT 2016 https://en.wikipedia.org/wiki/Standard_Delay_Format Entry: midi box Date: Wed Mar 16 11:19:31 EDT 2016 dedicated midi chip MFM0860 optocoupler? R 2701 L425 http://practicalusage.com/pu-1-lets-do-midi/ http://hackaday.com/2011/01/18/mcp2200-usb-to-serial-chip-hacked-to-do-your-bidding/ "I have a suspicion that the MFM0850 may just be a re-packaged Microchip 18F14K50." Entry: How to select a capacitor Date: Fri Apr 8 21:49:45 EDT 2016 https://blog.octopart.com/archives/2016/03/how-to-select-a-capacitor Entry: floating gate Date: Sun Apr 24 12:38:45 EDT 2016 http://www.rh.gatech.edu/news/508791/configurable-analog-chip-computes-1000-times-less-power-digital Entry: Pong P. Chu on FPGAs Date: Fri Apr 22 21:41:56 EDT 2016 And to clarify there are four excellent FPGA books from Pong P. Chu where the basic HDL sections are almost identical: Xilinx + Verilog: FPGA Prototyping by Verilog Examples:Xilinx Spartan-3 Version (2008) Xilinx + VHDL: FPGA Prototyping by VHDL Examples:Xilinx Spartan-3 Version (2008) Altera + Verilog: Embedded SoPC Design with Nios II Processor and Verilog Examples (2012) Altera + VHDL: Embedded SoPC Design with Nios II Processor and Verilog Examples (2011) -- M Entry: OSH Park Date: Sun Apr 24 01:45:07 EDT 2016 https://oshpark.com/ Entry: Implementing SPI: some design considerations. Date: Fri Jun 10 13:19:53 EDT 2016 1. Determine whether to clock the SPI state machine from the external or the internal clock. http://www.fpga4fun.com/SPI2.html: "Since the SPI bus is typically much slower than the FPGA operating clock speed, we choose to over-sample the SPI bus using the FPGA clock. That makes the slave code slightly more complicated, but has the advantage of having the SPI logic run in the FPGA clock domain, which will make things easier afterwards." It seems best to follow this setup. If SPI clock is in a different clock domain than main clock, add synchronizer FFs to clock and serial in. 2. State transitions Entry: metastability and derived clocks Date: Mon Jun 20 15:39:04 EDT 2016 72MHz STM32 clock -> 36MHz FPGA clock (STM32 timer). There might be a problem with this as signals generated by STM32 will change state at exactly the same time as the main FPGA clock edge. So if FPGA is clocked on posedge of timer, and bus writes are on posedge as well, we have an issue... If this is a problem, inverting the clock would fix it. Entry: those damn tools Date: Tue Jun 21 20:31:52 EDT 2016 So why is development so slow? Tools are clumsy, and too heterogenous. Too much patchwork and glue is necessary to get the cruft out of the way. Is there anything to do about this? Entry: linux/usbmon/wireshark debugging Date: Fri Jul 8 21:12:19 EDT 2016 - moprobe usb - tcpdump -D - tcpdump -i usbmon1 http://www.makelinux.net/ldd3/chp-13-sect-3 URB = USB request block https://ask.wireshark.org/questions/11054/analysing-usb-traffic To make sense of this it's probably enough to ignore USB_SUBMIT and only look at USB_COMPLETE packets. Entry: SPI modes Date: Mon Aug 1 13:50:19 EDT 2016 http://electronics.stackexchange.com/questions/29037/tradeoffs-when-considering-spi-or-i2c SPI has 4 possible modes for clock/data polarity, and two of them dominate -- almost all SPI devices update their MISO output on the falling edge of a clock and read their MOSI input on the rising edge of a clock. So if there is a choice, pick: - write edge 1->0 - read edge 0->1 and pick write edge before read edge, so idle=1 Implementing CPHA=1 in hardware is easy: write edge comes before read edge. CHPH=0 is harder because the first write edge is actually non-existant, and the last clock edge in a transfer is not used. Data needs to be set up before the first clock arrives. If bit 0 needs to be written by a slave, it should be written when CS goes low. However it seems that for many slave devices, the packet data has a request/reply structure, meaning the bits corresponding to the command traveling in the other direction are dont-care. Entry: resets Date: Tue Aug 2 15:07:07 EDT 2016 http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf Entry: setup and hold time Date: Wed Aug 3 00:09:39 EDT 2016 http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time Fundamental to operation is the 2-latch structure. Clock = 0 : first pass, second latches Clock = 1 : first latches, second passes Question: if the output feeds back to the input through a combinatorial circuit with a propagation delay less than the setup time, isn't that a problem? Or is the propagation delay through the second phase always more than the hold time? From this: http://www.cs.wustl.edu/~roger/260M.f13/CSE260M-Timing.pdf It seems that indeed hold time violations can occur if the combinatorial circuit is too fast. But it says also: In FGPAs, it is often the case that hold time < (min FF prop. delay) – (max clock skew) so, hold time violations cannot occur Prose: So I started digging into the reason why sequential logic actually works, e.g. why it is possible that you can drive a FF with a signal that is derived from another FF. This seems nonsensical if you look at the whole metastable problem, where you don't sample when somebody else is writing because it causes setup and hold time violations. Now, why then would a signal that changes on an edge be fed into a FF that samples on the same edge? Makes no sense right? Paradox. The reason is: For FF feeding into FF, e.g. in a shift register, the propagation delay to the output of the FF ensures that the hold time on the input is not violated. So the fact that propagation delay is finite and larger than the hold time is actually _essential_ to how these things work. Entry: Double DFF to combat metastability Date: Wed Aug 10 13:01:26 EDT 2016 The rationale: - If there is an edge that causes a timing violation, it is assumed that the oscillation that this might cause in the first DFF will settle before it would violate the setup time of the second DFF. - In case the first DFF settles to the incorrect edge, it will pass through the correct edge on the next clock. Entry: logic analyzer Date: Fri Aug 12 16:28:59 EDT 2016 Now that iCE is accessible for programming, what about adding a logic and/or protocol analyzer? Problem is still a fast pipe into a linux machine. Otherwise it needs to have some decoding already. Actually I do have those other FPGA boards as well, e.g. the openbench logic sniffer, which as a 18F chip. Staapl playground? Entry: pi sd cards Date: Sun Aug 14 00:14:40 EDT 2016 http://www.jeffgeerling.com/blogs/jeff-geerling/raspberry-pi-microsd-card Entry: 4 relay module Date: Mon Aug 15 19:39:33 EDT 2016 Doesn't work with 3V input, so use a 5V board. http://www.hobbyist.co.nz/?q=taxonomy/term/29 Entry: PIC DIP28 MINI KIT Date: Mon Aug 15 20:13:47 EDT 2016 Came with 16F876A which has no USB but is otherwise pin-compatible with 18F2550. Can I just plug in the latter? Looks like it.. http://www.ebay.com/itm/PIC-Development-Board-for-DIP28-PICs-PIC16F882-microcontrollers-Microchip-/310787936071 Entry: Long USB cables? Date: Tue Aug 16 00:43:38 EDT 2016 USB over CAT5 - not sure how these work. Active extenders up to 5M. Where does the range limitation come from? Has to do with reflections, but additional chaining limitation on reply delays? Entry: gpios on linux Date: Fri Aug 19 01:09:23 EDT 2016 To use low-level peripheral access, mmap /dev/mem (physical memory). Ordinarily a process only has virtual memory. http://www.righto.com/2016/08/the-beaglebones-io-pins-inside-software.html Entry: rs485 info Date: Wed Aug 24 23:06:39 EDT 2016 http://electronics.stackexchange.com/questions/33455/is-cat5-cable-good-enough-for-rs-485-vs-true-rs-485-cable https://www.maximintegrated.com/en/app-notes/index.mvp/id/3884 Entry: INTELLON 6300 Homeplug AV 200Mbps Date: Wed Aug 24 23:32:21 EDT 2016 http://www.zibri.org/2009/03/powerline-ethernet-fun-and-secrets.html Entry: battery-less doorbells Date: Sun Sep 4 12:19:53 EDT 2016 Uses kinetic energy to power the transmission. http://www.electronicsweekly.com/blogs/gadget-master/general/wireless-doorbell-rings-with-kinetic-energy-2016-03/ Cherry energy harvesting switch. http://www.extremetech.com/electronics/145728-nxp-and-cherry-team-up-to-make-an-energy-harvesting-wireless-light-switch Entry: 12V relays Date: Mon Sep 5 14:26:23 EDT 2016 Received the wrong kind (12V instead of 5v). But it looks like these can still be driven from 5V/3V, it just needs a 12V supply to drive the relay. They use opto couplers to drive a transistor that drives the relay current from the provided voltage JD-VCC voltage. https://www.sunfounder.com/wiki/index.php?title=4_Channel_5V_Relay_Module library://4_channel_relay_schematic.png md5://f1281597e5e8a8b0b721f9bc3808caf5 library://4_channel_relay_PCB.png md5://d1444c443d1b708481cd635566f3b6e6 So it's quite easy to change the driving voltage by connecting VCC to e.g. 3V, and JD-VCC to 5V, 12V, ... This schematic is inverting and corresponds to the 12V boards (marked HW-316). The first one I had (unmarked) is non-inverting. It has IN-R-OPTO-LED-GND on the input side. Entry: 2-way current loop Date: Fri Sep 9 14:20:19 EDT 2016 Is it possible? The main point of using an opto coupler is to decouple the ground at the receiver end. Looks like the problem is to switch the receiving diode out. Doesn't look very practical because there's a floating switch involved. Entry: Flash erase vs. write Date: Sun Oct 9 15:59:46 EDT 2016 Write is simple: you drain the cell. Erase is hard, as it tends to charge the cells around it. https://www.youtube.com/watch?v=MC1EKLQ2Wmg Entry: Hardware watchdog Date: Mon Oct 31 15:04:22 EDT 2016 ARM -> usb -> PIC18 -> relay board. ARM sends periodic "ok" messages to PIC. When these messages do not arrive withing a pre-determined time, PIC power-cycles the board. Meaning of "ok": ARM is functioning properly: - IP connection up - USB bus ok Entry: Vybrid M4 Date: Sun Nov 6 13:58:09 EST 2016 https://falstaff.agner.ch/2014/07/09/vybrid-bare-metal-fun/ Entry: Vybrid USB Date: Wed Nov 9 10:09:12 EST 2016 - controller can enable/disable external power: might be interesting for USB development. Entry: Vybrid GPIOs Date: Wed Nov 9 12:38:49 EST 2016 Something that keeps confusing me. Difference between: - PTA0, PTB1, ... naming scheme - GPIO_0 - GPIO_134 naming scheme - the 5 gpu controllers Toradex colibri som manual: The mapping between the port name (e.g. PORT0[27]) and pad name (e.g. PTB5) of the GPIO can be found in the same table in section 4.4. PAD_83 PORT2[19] PTD4 Entry: start from known config Date: Mon Nov 21 16:35:27 EST 2016 # cd /sys # find devices -name 'ttyACM?' devices/platform/soc/soc:aips-bus@40000000/40034000.usb/ci_hdrc.0/usb1/1-1/1-1.1/1-1.1:1.0/tty/ttyACM0 devices/platform/soc/soc:aips-bus@40000000/40034000.usb/ci_hdrc.0/usb1/1-1/1-1.2/1-1.2:1.0/tty/ttyACM1 devices/platform/soc/soc:aips-bus@40000000/40034000.usb/ci_hdrc.0/usb1/1-1/1-1.3/1-1.3:1.0/tty/ttyACM2 devices/platform/soc/soc:aips-bus@40000000/40034000.usb/ci_hdrc.0/usb1/1-1/1-1.4/1-1.4:1.0/tty/ttyACM3 Entry: Neutralize ME on X220 Date: Sun Nov 27 08:51:22 EST 2016 http://hardenedlinux.org/firmware/2016/11/17/neutralize_ME_firmware_on_sandybridge_and_ivybridge.html This is fairly recent work. Give it some time and it might end up in libreboot. other: http://www.slideshare.net/codeblue_jp/igor-skochinsky-enpub Entry: FPGA serdes Date: Sun Jan 1 19:51:22 EST 2017 Reason this exists is to avoid having to deal with bit clocks directly in the FPGA, but have a separate hardcoded peripheral do the serial to parallel conversion. Entry: KiCad, DipTrace Date: Thu Jan 19 23:12:47 CET 2017 http://hackaday.com/2017/01/19/autodesk-moves-eagle-to-subscription-only-pricing/ http://www.diptrace.com/ Entry: i2c combined transactions in linux Date: Mon Feb 13 11:08:07 EST 2017 Many devices use I2C repeated start conditions to perform read operations, where the address is sent by the master, then the reply is sent back by the slave. This needs ioctl I2C_RDWR -- the standard fd read/write is not enough. http://stackoverflow.com/questions/35078131/why-repeated-start-based-i2c-operation-are-not-supported-in-linux http://stackoverflow.com/questions/505023/reading-writing-from-using-i2c-on-linux Entry: Ajna light Date: Tue Apr 18 22:04:06 EDT 2017 10W LED x 5 5000 lument total 4N06L07 GRF523 mosfet Entry: Pulsed LED power supply Date: Wed Apr 19 22:55:01 EDT 2017 What if it were simpler to create a pulsed supply and use it to create brightness profile, than to gate a constant supply with a mosfet. Googling, some more about current vs. brightness curves - not what I wanted. https://electronics.stackexchange.com/questions/17528/does-pulsing-an-led-at-higher-current-yield-greater-apparent-brightness It seems better to go for switched current sources like: http://www.linear.com/product/LT3518 The 15uH power inductor seems expensive comparted to rest of circuit. This is likely why using a series resistor is still a common thing. The other LED light I have uses R-L-L-L series, equally distributed. Doing the same for a 10W LED (1A, 9V) with 3V resistor drop would require a 3Ohm, 3Watt resistor. That is a lot. Ajna light material is pretty woo-woo. Looking for some clearer material, found this: Dr.med. Dipl.-Psych. Dirk Proeckl https://www.vice.com/en_uk/article/futur-humans-lucia-LED-psychedelic http://old.ilacolor.org/node/523 http://www.lucialightexperience.com/development.html Hmm not less wonky. EDIT: current mode converters http://www.ti.com/lit/an/snva555/snva555.pdf Q: - in a current-mode buck converter, why is there a capacitor? it filters the ripple current. for LED driver, ripple might not be important? I found at least one circuit that doesn't have the cap, and uses a switch to ground to charge the inductor. Circuit could be calibrated to run in feedforward PWM only. https://www.digikey.com/en/articles/techzone/2011/jun/buck-regulators-make-driving-high-brightness-leds-easy - how to pick an inductor? http://www.ti.com/lit/an/snva038b/snva038b.pdf higher frequencies allow for smaller inductors, but create more switching losses. where is the optimum? Entry: cordless vac battery died Date: Wed Jun 14 14:36:50 EDT 2017 6V - I wonder what this draws. Has NiCd Replacement NiMH is 2200mAh Would need 5x Entry: 44-pin pata 2.5" drives Date: Sat Jun 17 16:36:08 EDT 2017 Pin 20 is KEY. I had to remove that pin on the CF to PATA adapter to allow it to plug into the PATA to USB adapter. http://paulski.com/zpages.php?id=1717 Entry: A decent audio transport Date: Fri Jul 14 19:30:51 EDT 2017 What about using SPDIF or something similar over CAT5e? It shouldn't be too hard to make that work. TCP really sucks. UDP might work for dedicated link. But I wonder. Why not a simple digital protocol. There are commercial solutions. But even simpler: analog: https://www.jeffgeerling.com/articles/computing/2015/everything-over-cat5#audio https://www.jeffgeerling.com/articles/audio-video/xlr-mic-level-balanced-audio-over-cat5e So that should not be a problem. Still I like the idea of using Ethernet in some kind of low-latency broadcasting setup. Maybe learn how to use RTSP/RTP? EDIT: works with vlc as streamer and also with dedicated RTP .c program. Works well on Ethernet, but forget it on wifi. Entry: Turn power supply into class D amp Date: Fri Jul 14 21:01:26 EDT 2017 Bus voltage -> bus volume Turn one of those STM32F103 into a USB AUDIO -> PWM converter. Entry: STM32F4 Date: Mon Aug 7 12:31:56 EDT 2017 - axoloti: STM32F405RGT6 - discovery: STM32F407VGT6 - ebay: STM32F407VET6 http://www.st.com/en/microcontrollers/stm32f4-series.html?querycriteria=productId=SS1577 STM32F407/417 – 168 MHz CPU/210 DMIPS, up to 1 Mbyte of Flash memory adding Ethernet MAC and camera interface STM32F405/415 – 168 MHz CPU/210 DMIPS, up to 1 Mbyte of Flash memory with advanced connectivity and encryption Entry: Hacking existing midi controllers Date: Sat Nov 11 14:11:29 EST 2017 Rip out the guts and put own conttroller + firmware. I don't need midi. Entry: staapl sheepsint Date: Sun Dec 10 17:54:55 EST 2017 Combine it with brute filter input. It can go on the mixer, there's one free channel. Entry: Thermostat Date: Sun Jan 7 19:20:43 EST 2018 1. Strip wires without cutting and add a tap 2. Run this to some other point where an STM103 or PIC board can be attached to USB. Actually I only need to implement the "or" operation and the information transport. I can use off-the shelf thermostats. So what's needed? An access point from the wire to a relay board, to a uC, to USB to a PC to net. Figure out which one should be the long wire. <- 2-strand 25V~ -> relay board <- 2-strand 5V+- -> pic board <- USB -> linux pc <- Ethernet -> hub Or, I can make it wireless and use one of those ESP thingies. I'll likely need to do that with the thermostat also. ESP8266 Or use a serial / RS485 line. I'm going to do this on an ARM board with Ethernet. Time to get my "platform" to work. I have one. More can be gotten later. Entry: 2-Wire Thermostat Wiring Date: Wed Jan 10 14:14:27 EST 2018 I'm thinking mine is wired wrong. B=black W=yellow Everything I find is to use R instead of B. I can't find why it would work though the way it is wired. But, to augment the circuit, I just need to add a relay in parallel, so none of this really matters. Entry: 802.11b simplest modulation? Date: Fri Jan 26 22:18:59 EST 2018 https://en.wikipedia.org/wiki/IEEE_802.11b-1999 https://www.eetimes.com/document.asp?doc_id=1295161 Entry: Bit-bang Ethernet Date: Sat Jan 27 23:34:38 EST 2018 Requires 20Mbit stream out to perform Manchester encoding. SPI would work. But generating the packets will take some effort. https://en.wikipedia.org/wiki/Manchester_code Electrical, see figure 6: https://www.nxp.com/docs/en/application-note/AN2759.pdf Entry: FM loop antenna Date: Sat Feb 10 15:11:30 CET 2018 US: circular polarization? diagonal (* 2.54 48) 120m Maar hier: https://www.circuitsonline.net/forum/view/47949 3m band, dipool impedantie 50ohm Entry: online speaker phase test Date: Mon Feb 12 22:34:56 CET 2018 http://www.audiocheck.net/audiotests_polaritycheck.php Entry: skytoppower STP6005 Date: Wed Mar 28 11:41:40 EDT 2018 These do not handle shorting! Fuse blew. Made room lights flicker. F6A250 replaced with F2A250 but blew immedately on power on. Ordering new F6A250 Entry: HID instead of serial port Date: Wed Mar 28 21:06:46 EDT 2018 Why use HID? https://github.com/darrylb123/usbrelay/blob/master/usbrelay.c Entry: HY3003D power supply Date: Wed Apr 4 17:04:06 EDT 2018 Problem seems to be noisy potentiometer for the voltage controll. Moving it back&forth a couple of times seems to fix the issue. Also measured on scope to check overshoot, but didn't see any. Overshoot on display is likely just the voltmeter. This power supply uses an analog control voltage, and a volt+amp meter for user interaction. The voltage is not set digitally! Entry: USB relay board Date: Tue Apr 10 11:39:24 EDT 2018 [1052942.837256] usb 2-4.4.4.3: new low-speed USB device number 92 using ehci-pci [1052942.973670] usb 2-4.4.4.3: New USB device found, idVendor=16c0, idProduct=05df [1052942.973716] usb 2-4.4.4.3: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [1052942.973721] usb 2-4.4.4.3: Product: USBRelay2 [1052942.973725] usb 2-4.4.4.3: Manufacturer: www.dcttech.com [1052942.978432] hid-generic 0003:16C0:05DF.0061: hiddev0,hidraw2: USB HID v1.01 Device [www.dcttech.com USBRelay2] on usb-0000:00:12.2-4.4.4.3/input0 [1052943.031331] media: Linux media interface: v0.10 [1052943.038764] Linux video capture interface: v2.00 [1052943.040142] usbcore: registered new interface driver radio-ma901 https://github.com/darrylb123/usbrelay 16c0:05df https://usb-ids.gowdy.us/read/UD/16c0/05df Free USB HID/PID pair for use with V-USB projects, ideally requiring software to be open-source. Masterkit MA901 USB radio apt-get install usbrelay root@zoe:~# usbrelay Device Found type: 16c0 05df path: /dev/hidraw2 serial_number: Manufacturer: www.dcttech.com Product: USBRelay2 Release: 100 Interface: 0 Number of Relays = 2 BITFT_1=0 BITFT_2=0 Entry: Scroll device Date: Sun Apr 15 17:48:08 EDT 2018 3 rotaries 2 for mouse x/y 1 for scroll wheel Entry: Colibri board Date: Fri May 4 13:43:56 EDT 2018 Currently set up with boot console on these pins of Extension Connector (X9) 24 GND 26 UART_A_TXD +3.3V 27 UART_A_RXD +3.3V Other serial port (used for gateway, phytec). 36 UART_B_TXD O +3.3V 37 UART_B_RXD I +3.3V 40 GND 2 50 1 49 ---- edge ---- https://developer.toradex.com/products/viola-carrier-board https://docs.toradex.com/102879-colibri-arm-viola-carrier-board-datasheet.pdf Currently set up with TFTP boot as default. Probably easiest to run Debian on this one. With SD card that will not be a problem. Then the NAND can keep the original Angstrom. NAND bootloader can boot from sdcard. It needs image in /boot/zImage Where to get that kernel? Using https://developer1.toradex.com/files/toradex-dev/uploads/media/Colibri/Linux/Images/Colibri-VF_Console-Image_2.8b2.97-20180331.tar.bz2 run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} ${vidargs}; load mmc 0:1 ${kernel_addr_r} zImage load mmc 0:1 ${fdt_addr_r} vf610-colibri-eval-v3.dtb run fdt_fixup bootz ${kernel_addr_r} - ${fdt_addr_r} getty is not available on tty1 Probably should configure dhcp. Ok, was already configured. I can log in and have outgoing network access.. Next: fix up bootloader. setenv debboot 'run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} ${vidargs}; load mmc 0:1 ${kernel_addr_r} zImage; load mmc 0:1 ${fdt_addr_r} vf610-colibri-eval-v3.dtb; run fdt_fixup; bootz ${kernel_addr_r} - ${fdt_addr_r}' setenv bootcmd 'run debboot' saveenv Entry: Viola outputs Date: Fri May 4 19:46:18 EDT 2018 3 naming schemes: - Viola Carrier Board Extension Connector (X9) https://docs.toradex.com/102879-colibri-arm-viola-carrier-board-datasheet.pdf - SODIMM pins are described here: https://docs.toradex.com/101355-colibri-vf61-datasheet.pdf - GPIO pins as they appear on the X9 Viola connector. PORTx[y] = gpio(32*x+y) relay X9 Colibri SODIMM name gpio ---------------------------------------------------- 1 8 SODIMM_135 (GPIO) PTD10 gpio89 2 9 SODIMM_98 (GPIO) PTC1 gpio46 3 10 SODIMM_133 (GPIO) PTD9 gpio88 4 11 SODIMM_103 (GPIO) PTC3 gpio48 info on using pins: https://developer.toradex.com/getting-started/module-3-hardware-peripherals/basic-gpio-usage-colibri-evaluation-board-colibri-vfxx uC draws 70mA more @5V when pin is asserted. This is no good. Put a resistor in series? EDIT: Actually this is relay drive current. The GPIOs drive only 1kOhm with a 1V opto coupler diode in series, around 2mA With 4 relays on, the current limit on the power supply was triggered. Entry: Splitter box for TV? Date: Fri May 4 21:34:33 EDT 2018 Basically, allow TV to be off. PC -> TV -> mixer Roku -> TV -> mixer Maybe tv audio in should just be the mixer out? Entry: Longer relay wires Date: Fri May 4 21:42:20 EDT 2018 I want to turn the speakers on/off but they are too far away from the control computer. I could run 120V lines, but it seems to make more sense to run the 5V or 12V relay actuator signal to the other end. But.. that does away with the isolation. So best to keep the actuation on the other end. Entry: Generic bit-bang setup Date: Thu May 10 17:48:00 EDT 2018 Maybe do this also in Rust. For testing purposes, set up bit-bang interfaces. Maybe a good exercise for Rust on STM, because this will need access to accurate timing. Is it possible to set up a timer interrupt on the beaglebone? To do this on linux seems asking for trouble... Entry: Thermometer board STM32 Date: Mon May 14 17:00:25 EDT 2018 A good target for rust. Entry: Minijack serial connector convention. Date: Sat May 19 11:54:09 EDT 2018 First one i find on amazon: sleeve = GND ring = RX tip = TX Entry: Light switch broke Date: Tue May 22 20:48:10 EDT 2018 Seems melted. Happened after plugging in iron + steamer in the same circuit. How can this happen? Some resistance in there that is large enough to cause some dissipation, but not large enough to limit the current relative to the other resistor in series? With a low-resitance load, the heat dissipation goes up. Maybe this was happening a lot already, just now the current was high enough to heat it up until it deformed, breaking the circuit? Entry: zoe crashes Date: Sun Jun 10 17:44:54 EDT 2018 I've not seen any crashes since I moved the USB devices to nexx2, but now I see problems on nexx. I think the issue is due to the device being powered down while a TTL cable is attached. It makes little sense, because there is a 270R current limiting resistor in the cable. (/ 3.3 270) is 12mA Using the cp210x device is better, but device still resets usb on bbb power cycle. Entry: Linux on STM32F7 Date: Tue Jun 12 16:45:03 EDT 2018 I thought this line was Cortex M only? Apparently there are boards with SDRAM. https://elinux.org/STM32#STM32F7_based Entry: Reusing circuitry Date: Fri Jun 15 20:48:21 EDT 2018 So I've made some dedicated things, which is easy to do. Next challenge is to make some more complex multi-function circuits. I'm starting to understand the idea of a bus: it is a central mux-point to connect any producer in the system with a consumer. So the way I would approach this, is as a multiplexer. The current address register selects one of the producers in the system. However, it seems often this is implemented using tristate logic: a device asserts the bus when it's address is present. http://dev.myhdl.org/meps/mep-103.html#modeling-a-tristate-bus-as-a-module Is it actually a good idea on an FPGA to do this? https://news.ycombinator.com/item?id=14935204 http://fpgasite.blogspot.com/2017/05/fpga-internal-tri-state-buses.html It seems that designs are optimized for unidirectional signals, with tristate signals eliminated. So that's clear: no data bus, but muxes. Fits better in a "functional" design as well. Entry: SRAM Date: Sat Jun 16 17:49:35 EDT 2018 https://electronics.stackexchange.com/questions/144986/schematic-for-run-of-the-mill-sram wordline: decoded from address bitline: one for each bit of the memory a read will not assert the bitline a write will assert the bitline ignoring any output latching, reading and writing the same address is a pass-through operation. now, how does a clocked ram work? Synchronous SRAM. Entry: Latch vs flipflop Date: Sat Jun 16 17:53:46 EDT 2018 Latches on FPGA? https://electronics.stackexchange.com/questions/21887/difference-between-latch-and-flip-flop So not a good idea on FPGAs. Latches are considered 'bad' because - Latches are almost always unintentionally inferred by poorly written source code - FPGA timing tools (and timing based place/route algorithms) are single-mindedly oriented to register-based design Entry: VHDL delta-time Date: Wed Jun 20 23:00:00 EDT 2018 Apparently, VHDL uses a sort of "infinitesimal" time step to resolve signals that have unclocked feedback loops (latches?). https://www.researchgate.net/publication/242599776_The_discrete_event_simulation_semantics_of_VHDL So can you implement a D flipflop in VHDL using only latches? Entry: Multi-UART design Date: Tue Jul 17 20:43:14 EDT 2018 The basic idea is to sync at the start bit 0->1 transition, then sample the next 9 bits at the middle bit. If there are many different UARTS, all with the same baud rate and main FPGA clock, it makes sense to attempt to derive them from a shared baud clock. How much oversampling is needed? I.e. 1x is not enough, because it cannot see the middle of the bit 2x can be problematic if we caught the edge late 3x seems the first appropriate choice that is symmetric wrt the edge mismatch distribution, and has some margin wrt the edge case, leaving 1/3 bit width for drift. 0 is edge, sample at phase 1. The expected value value of the edge mis-detection is half a sample period. For example, a 4-bit AR with 1 start, 1 stop bit. Below is the display for perfect 3x oversampling. Sampling in the middle of the bit allows for edges to drift forward and backward. This seems safest. Other guarantees might be possible? 111 000 aaa bbb ccc ddd 111 000 aaa bbb ccc ddd 111 ..... [ 0 1 2 3 ] [ 0 1 2 3 ] 4x would use the same amount of bits This mentions to oversample at 16x: https://electronics.stackexchange.com/questions/207870/uart-receiver-sampling-rate This mentions 8x https://www.fpga4fun.com/SerialInterface4.html Power-of-two makes the logic simpler. So let's just stick to 8x. The difference with 4x is only one bit. Entry: NPN + bias resistors Date: Tue Jul 31 12:51:17 EDT 2018 From BBB schematic. Has 2xNPN + bias resistors. DMC56404 https://industrial.panasonic.com/content/data/SC/ds/ds4/DMC56404_E.pdf Entry: FT90x FTDI chip Date: Sun Aug 5 22:15:06 EDT 2018 Architecture name is ft32 Swapforth runs on this thing. So what is it? http://www.ftdichip.com/MCU.html http://www.ftdichip.com/Products/ICs/FT90x.html Entry: topcom pabx clx206-b Date: Wed Aug 8 15:12:58 EDT 2018 https://www.scribd.com/document/288334917/Clx206-F md5://d97090ae43a94fe1f08d30e7d593f1cd topcom-Clx206-F.pdf Entry: Where are my electronics courses? Date: Thu Aug 9 23:02:30 EDT 2018 I guess look for them on the next trip over. Here's what I want to read: trade-offs between parallel and serial. We covered at least: - special-purpose sequencing (e.g. filter) - bit-serial designs - pipelining Entry: bit-serial Date: Thu Aug 9 23:25:13 EDT 2018 https://en.wikipedia.org/wiki/Bit-serial_architecture Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor. Random google link: http://www.andraka.com/files/fir.pdf The time-hardware product, however, for the serial structure is often smaller than for equivalent parallel designs because the logic delays between registers are generally significantly smaller. Entry: Serial adder Date: Tue Aug 28 03:53:14 EDT 2018 Straightforward. The only difficulty is in resetting the carry bit at word boundaries. Entry: BeagleWire Date: Fri Aug 31 13:28:10 EDT 2018 P9_28,C12,SPI1_CS0,0x19C,mcasp0_ahclkr,ehrpwm0_synci,mcasp0_axr2,spi1_cs0,eCAP2_in_PWM2_out,pr1_pru0_pru_r30_3,pr1_pru0_pru_r31_3,gpio3_17,, P9_29,B13,SPI1_D0,0x194,mcasp0_fsx,ehrpwm0B,-,spi1_d0,mmc1_sdcd,pr1_pru0_pru_r30_1,pr1_pru0_pru_r31_1,gpio3_15,, P9_30,D12,SPI1_D1,0x198,mcasp0_axr0,ehrpwm0_tripzone,-,spi1_d1,mmc2_sdcd,pr1_pru0_pru_r30_2,pr1_pru0_pru_r31_2,gpio3_16,, P9_31,A13,SPI1_SCLK,0x190,mcasp0_aclkx,ehrpwm0A,-,spi1_sclk,mmc0_sdcd,pr1_pru0_pru_r30_0,pr1_pru0_pru_r31_0,gpio3_14,, Should be straightforward to configure. Does it clash with anything? SDRAM is too much work to use, but GPMC might be interesting to explore. Also takes a bit of work. So for now, there is no direct use for it. Plug it into the bbb and set it up for programming. SPI Flash is not hooked up properly either. iCE40 can't boot from this. What else is on that GPMC port? AD0-15 ADVN BEON CSN1 CLK WEIN OEN P8_3,R9,GPIO1_6,0x018,gpmc_ad6,mmc1_dat6,-,-,-,-,-,gpio1_6,, P8_4,T9,GPIO1_7,0x01C,gpmc_ad7,mmc1_dat7,-,-,-,-,-,gpio1_7,, P8_5,R8,GPIO1_2,0x008,gpmc_ad2,mmc1_dat2,-,-,-,-,-,gpio1_2,, P8_6,T8,GPIO1_3,0x00C,gpmc_ad3,mmc1_dat3,-,-,-,-,-,gpio1_3,, P8_7,R7,TIMER4,0x090,gpmc_advn_ale,-,timer4,-,-,-,-,gpio2_2,, P8_8,T7,TIMER7,0x094,gpmc_oen_ren,-,timer7,-,-,-,-,gpio2_3,, P8_9,T6,TIMER5,0x09C,gpmc_ben0_cle,-,timer5,-,-,-,-,gpio2_5,, P8_10,U6,TIMER6,0x098,gpmc_wen,-,timer6,-,-,-,-,gpio2_4,, P8_11,R12,GPIO1_13,0x034,gpmc_ad13,lcd_data18,mmc1_dat5,mmc2_dat1,eQEP2B_in,pr1_mii0_txd1,pr1_pru0_pru_r30_15,gpio1_13,, P8_12,T12,GPIO1_12,0x030,gpmc_ad12,lcd_data19,mmc1_dat4,mmc2_dat0,eQEP2A_IN,pr1_mii0_txd2,pr1_pru0_pru_r30_14,gpio1_12,, P8_13,T10,EHRPWM2B,0x024,gpmc_ad9,lcd_data22,mmc1_dat1,mmc2_dat5,ehrpwm2B,pr1_mii0_col,-,gpio0_23,, P8_14,T11,GPIO0_26,0x028,gpmc_ad10,lcd_data21,mmc1_dat2,mmc2_dat6,ehrpwm2_tripzone_in,pr1_mii0_txen,-,gpio0_26,, P8_15,U13,GPIO1_15,0x03C,gpmc_ad15,lcd_data16,mmc1_dat7,mmc2_dat3,eQEP2_strobe,pr1_ecap0_ecap_capin_apwm_o,pr1_pru0_pru_r31_15,gpio1_15,, P8_16,V13,GPIO1_14,0x038,gpmc_ad14,lcd_data17,mmc1_dat6,mmc2_dat2,eQEP2_index,pr1_mii0_txd0,pr1_pru0_pru_r31_14,gpio1_14,, P8_17,U12,GPIO0_27,0x02C,gpmc_ad11,lcd_data20,mmc1_dat3,mmc2_dat7,ehrpwm0_synco,pr1_mii0_txd3,-,gpio0_27,, P8_18,V12,GPIO2_1,0x08C,gpmc_clk,lcd_memory_clk,gpmc_wait1,mmc2_clk,pr1_mii1_crs,pr1_mdio_mdclk,mcasp0_fsr,gpio2_1,, P8_19,U10,EHRPWM2A,0x020,gpmc_ad8,lcd_data23,mmc1_dat0,mmc2_dat4,ehrpwm2A,pr1_mii_mt0_clk,-,gpio0_22,, P8_21,U9,GPIO1_30,0x080,gpmc_csn1,gpmc_clk,mmc1_clk,pr1_edio_data_in6,pr1_edio_data_out6,pr1_pru1_pru_r30_12,pr1_pru1_pru_r31_12,gpio1_30,,Output P8_22,V8,GPIO1_5,0x014,gpmc_ad5,mmc1_dat5,-,-,-,-,-,gpio1_5,,Input P8_23,U8,GPIO1_4,0x010,gpmc_ad4,mmc1_dat4,-,-,-,-,-,gpio1_4,,I/O P8_24,V7,GPIO1_1,0x004,gpmc_ad1,mmc1_dat1,-,-,-,-,-,gpio1_1,, P8_25,U7,GPIO1_0,0x000,gpmc_ad0,mmc1_dat0,-,-,-,-,-,gpio1_0,, not used: P8_20,V9,GPIO1_31,0x084,gpmc_csn2,gpmc_be1n,mmc1_cmd,pr1_edio_data_in7,pr1_edio_data_out7,pr1_pru1_pru_r30_13,pr1_pru1_pru_r31_13,gpio1_31,, P8_26,V6,GPIO1_29,0x07C,gpmc_csn0,-,-,-,-,-,-,gpio1_29,, EDIT: SPI programming. They are following this approach: https://hackaday.io/project/7982-cat-board/log/36982-cat-board-all-on-its-own Mode 1 is the most difficult. The RPi pulls the SPI CS line low as it removes the reset from the FPGA. This places the FPGA in slave mode so the RPi can send a bitstream to the FPGA's SPI port. But this also enables the flash chip's SPI port, which means the flash's SO output could interfere with the bitstream data. Unfortunately, there's no reset pin on the flash to keep it quiet. However, the flash does have a deep power-down mode that is entered by sending a specific command to the flash. Once in this state, it will not respond to anything until it receives another specific command to wake up. The RPi can then transfer the bitstream to the FPGA. During the transfer, there's no chance the wake-up command will be sent accidentally to the flash's SI input because 1) neither the RPi or FPGA will be driving that signal line during the configuration process, and 2) the flash only executes a command once its CS input goes high but the SPI CS line is held low for the entire duration of the bitstream transfer. So the flash will stay quiet and the RPi can send the bitstream to the FPGA in peace. The loader code is in the linux kernel: https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt https://hackaday.com/2017/04/13/lattice-ice40-fpga-configured-by-linux-kernel/ EDIT: The workaround is not currently implemented. EDIT: I think I'm not going to use this for now. The other dev board is much easier to use at this point, and I have currently no use for the SDRAM or GPMC. Entry: EEVBLOG #1015 center negative Date: Mon Sep 10 00:54:08 EDT 2018 This allows the barrel switch to be used to disconnect the + of an internal battery. Maybe this is why the guitar pedals use this convention? Entry: AM335x slew control Date: Mon Sep 10 01:51:56 EDT 2018 See Pad Control Registers in TRM Entry: SDRAM Date: Wed Sep 12 00:29:15 EDT 2018 https://hackaday.com/2013/10/11/sdram-controller-for-low-end-fpgas/ http://ladybug.xs4all.nl/arlet/fpga/source/sdram.v http://ladybug.xs4all.nl/arlet/fpga/ Entry: GPI and metastability Date: Thu Sep 13 21:21:23 EDT 2018 PRU docs say GPIs are "direct connect". Won't this lead to metastability? I don't see _any_ mention of synchronizer flip-flops anywhere, so I'm assuming this is true. ( Also because the clocked parallel capture explicitly mentions a synchronizer flipflop. ) So, let's assume this is the case. How can this not wreak havoc? Found this, suggesting that metastability issues can also be handled in "software", similar to how you would debounce a switch. Entry: Synth project Date: Sat Sep 15 10:04:14 EDT 2018 Instead of overthinking it, why not just build it? Basic architecture is a uC + stuff. Let's not worry about layout too much and use wire wrap. What I'm looking for mostly is an incremental way of working, keeping it simple. Essentially, USB should not be part of the synth. Use a serial port and be done with it. Put all communication hardware somewhere else. Reboot Staapl. Entry: FPGA and pulse-position controllers Date: Sat Sep 15 11:52:44 EDT 2018 Basically, lots of pins, and each pin could be a high frequency pulse modulator, to be used as an analog controller output. Entry: DML speakers Date: Sun Sep 16 20:02:48 EDT 2018 Orig youtube video: https://www.youtube.com/watch?v=zdkyGDqU7xA Distributed Mode Loudspeaker https://en.wikipedia.org/wiki/Distributed_mode_loudspeaker Dayton exciters https://www.daytonaudio.com/index.php/exciters-buyers-guide Also look into the other videos. Entry: dsPIC33FJ128GP802 Date: Mon Sep 17 00:09:04 EDT 2018 DIP with 2 DACs https://www.microchip.com/wwwproducts/en/dsPIC33FJ128GP802 Entry: dsPIC chips Date: Mon Sep 17 00:17:13 EDT 2018 What do I actually have in the box? old: dsPIC30F4013 x3 dsPIC30F3013 x6 dsPIC30F3012 x2 fike: dsPIC 33FJ128GP x7 dip x3 qfp Entry: about DIP packages Date: Wed Sep 19 20:54:50 EDT 2018 The dsPIC stuff is probably not going to happen. Strays too far. I'm probably just looking for someting exotic. Anwyays, there are NXP M0+ DIP8 packages: LPC810M021FN8 DIP8 4k/1k https://www.nxp.com/docs/en/data-sheet/LPC81XM.pdf So if it is DIP that I want for building boards, I should probably go with these. Will have much better software support. Code gen could still be done for ARM. And M0 DIP28: LPC1114FN28 DIP28 32k/4k https://www.nxp.com/docs/en/data-sheet/LPC111X.pdf https://hackaday.com/2015/10/09/arming-a-breadboard-everyone-should-program-an-arm/ Entry: Ethernet Date: Wed Sep 19 21:08:30 EDT 2018 I've been seeing these ENC28J60 SPI to 10MBit Ethernet chips everywhere. Is it worth it to add ethernet to a simple uC, or does it make sense to always go to a Linux-capable machine? http://ww1.microchip.com/downloads/en/DeviceDoc/39662e.pdf Also, this should be traded against RS485 or other busses with a hub-and-spokes 1-linux + many uC model. Entry: Maintenance on Fender amp PRO 185 Date: Sun Sep 30 16:00:41 CEST 2018 - clean channel or channel switch broken - some pots crackle or have bad segments - power section seems fine, all preamp issues https://elektrotanya.com/fender_185_series_029053f_pro_stage_london_sch.pdf/download.html Also md5://565fac55f1d36751ad2b33582566b709 Entry: ADAT Date: Mon Oct 1 02:07:14 CEST 2018 https://ackspace.nl/wiki/ADAT_project Entry: wax thermometer Date: Thu Oct 4 19:18:31 CEST 2018 I have something using a power diode 1N4004 The opamps I have are LM358P, which have 1.5V from top rail, 20mV from bottom, so circuit needs to take this into account. Esp current source needs NPN configuration. Input range is 0 to VCC-2. Design approach: - VG at around 3V, pulled down by voltage range. - VG not accurate, so do differential ADC measurement to compare output with VG. - NPN current source (based LM358P). Alternative (3): - PNP with emittor resistor to pull base down to < VCC-2 for LM358P. - current source reference derived from regulated 3.3V - measurement resistor at 0.5V = 0K point - difference added to 0.5V prob is ref resistor takes extra current Some more notes: There seem to be 2x2 reasonable configurations: - NPN or NPN current source - positive or negative output wrt. vground The reference for the current source should come from known voltage referenced to ground, this eliminates the NPN configuration. So what's left is up or down. Down doesn't have the problem where the amplifier current doesn't flow through the current source resistor. For PNP it's possible to lower the opamp control point by using a bias network. But going this route, it makes sense to eliminate the opamp, since current source is constant. EDIT: This makes it harder to use the 3.3V as reference. Summary: - 2x opamp in LM358P creates some constraints due to high rail saturation: VCC - 2V. This, together with 5V main rail and 3.3V regulator + analog inputs tips the symmetry. - Amp swings downward from VG at around 3.3V. - One opamp for amplifier, one for current source. Latter gives more flexibility to position the voltages, and makes it possible to use 3.3V input as reference. Entry: Thermometer Date: Fri Oct 5 11:24:39 CEST 2018 (/ 3.3 470) 7 ma Seems to work with: PNP bias network 1k/4k7 Gain 4k7/1k Meas resistor 470, Vref 3.3V 47uF between PNP B-E Without cap, it was oscillating at around 500kHz Surprise: voltage rises when temperature rises. This is also in the 1N4148 datasheet: forward voltage falls when temperature rises. (See next post). One thing: voltage drop over diode is very small. 40mV. Maybe because it is a large signal diode, and it takes a fairly small current: (/ 3.3 470) 7mA So how to calibrate? Lowest voltage is lowest temperature. Changed 4k7 gain to 10k. It should also be possible to inject some offset to use more of the usable range. I'm thinking about 300-400 K as useful range. At room temperature, the diode voltage is 400mV. Which is 0.4mA over 1k input resistor. To 3.3V this would be (/ 3.3 0.4) 9kOhm. So let's take half of that 22kOhm to ground from (-). So, assuming V-T is linear, this gives 2 resistors to set the measurement range. When building a circuit, make sure these can be easily replaced. Entry: Curve Date: Fri Oct 5 15:35:34 CEST 2018 Surprise: voltage lowers when temperature rises. This is what I see in the circuit. This is also in the 1N4148 datasheet: forward voltage falls when temperature rises. But looking at the V/I formula: I = I0 e^(qV/kT) When I is constant, this gives V~T So where am I going wrong? Proportional can mean negative. So this is likely about the constants. I = Is exp(qV/kT) ln(I/I0) = qV / kT Yes I just don't see it. If T rises, V rises, not the other way around. But everywhere I look it says diode has negative temperature coefficient. It is not in the equation above. The effect comes from Is, the reverse saturation current. https://en.wikipedia.org/wiki/Diode The reverse saturation current, IS, is not constant for a given device, but varies with temperature; usually more significantly than VT, so that VD typically decreases as T increases. So is there a formula? Not really. The point is that it is linear, and that it needs to be calibrated by taking two reference measurements. Here are some formulas: http://lampx.tugraz.at/~hadley/psd/L6/VT_I.php http://www.angelfire.com/planet/sft_accommodation/acu_semiconductor_diode_equations.htm "The intrinsic carrier density is a strong function of temperature" Entry: STM32F103 Date: Fri Oct 5 17:12:44 CEST 2018 ADC12_IN1 PA1 (also USART2_RTS, TIM2_CH2) Next: set up pins, read out. Entry: Current source Date: Sun Oct 7 11:25:52 CEST 2018 Can it be done simpler using just a transistor? The exact value of the current isn't as important as it being constant. Given that free opamp, this is already fairly optimal. Remaining: use a single base resistor. This depends on h_FE, which is specified 70-400. It seems best to just rely on v_BE, which is easier to aim for. Entry: Is that PNP really necessary? Date: Wed Oct 10 15:20:17 CEST 2018 Why not steer directly from opamp output? Typically that transistor is needed to mirror the current in the measurement leg and the source/sink leg. - current source amp: - diode between out and min - 3.3 on plus - inverting gain amp: - diode plus - R - amp min - R - amp out - diode min - amp plus (hinge point) Problem: output of LM358P is too high. Alternative: diode in feedback loop, which allows the voltage set point of the current source amp to be chosen more freely such that inputs and outputs of amp are within range. Offset at amplification stage can be chosen freely. - vref as R/2R 3.3 / 1.7V - diode current set based on voltage drop from 3.3 to 1.7 - gain determined by actual diode voltage drop - two inverting stages, so voltage drops per rising temp - which way to offset-compensate? Setting gains 2mV / K. Range is about 100K, so 200mV That is mapped into 3.3V range. But let's map it to half of that to allow some slack: 1500mV or about 10x gain. v_d' = 1.7 - v_d v_out = 1.7 - G/S v_d' + 1.7 G/O = 1.7 - G/S (1.7 - v_d) + 1.7 G/O = 1.7 (1 - G/S + G/O) + G/S v_d When temp rises, v_d drops, input current into vground drops, output offset drops. Problem with this circuit is that it's hard to calibrate one extreme, then calibrate gain. However, it is possible to calibrate the mid point, which would be around 50-65 deg C. How to calibrate? 1. Pick a diode current. This determines R_set 2. Determine midpoint voltage drop. Together with R_scale, this determines R_offset such that midpoint current through R_scale and R_offset cancel out. 3. R_gain can then be set independently Typical values: - 10k R/2R - 220 R_set (/ 1.7 220) 7mA - room temperature diode drop 400mV - R_scale 1K (initial guess) - (/ 1.7 0.4) 4.25 -> R_offset 4k7 - swing: (/ 1.7 0.2) -> 8.5 10k Entry: Current source Date: Sun Oct 7 11:25:52 CEST 2018 Can it be done simpler using just a transistor? The exact value of the current isn't as important as it being constant. Given that free opamp, this is already fairly optimal. Remaining: use a single base resistor. This depends on h_FE, which is specified 70-400. It seems best to just rely on v_BE, which is easier to aim for. Entry: Is that PNP really necessary? Date: Wed Oct 10 15:20:17 CEST 2018 Why not steer directly from opamp output? Typically that transistor is needed to mirror the current in the measurement leg and the source/sink leg. - current source amp: - diode between out and min - 3.3 on plus - inverting gain amp: - diode plus - R - amp min - R - amp out - diode min - amp plus (hinge point) Problem: output of LM358P is too high. Alternative: diode in feedback loop, which allows the voltage set point of the current source amp to be chosen more freely such that inputs and outputs of amp are within range. Offset at amplification stage can be chosen freely. - vref as R/2R 3.3 / 1.7V - diode current set based on voltage drop from 3.3 to 1.7 - gain determined by actual diode voltage drop - two inverting stages, so voltage drops per rising temp - which way to offset-compensate? Setting gains 2mV / K. Range is about 100K, so 200mV That is mapped into 3.3V range. But let's map it to half of that to allow some slack: 1500mV or about 10x gain. v_d' = 1.7 - v_d v_out = 1.7 - G/S v_d' + 1.7 G/O = 1.7 - G/S (1.7 - v_d) + 1.7 G/O = 1.7 (1 - G/S + G/O) + G/S v_d When temp rises, v_d drops, input current into vground drops, output offset drops. Problem with this circuit is that it's hard to calibrate one extreme, then calibrate gain. However, it is possible to calibrate the mid point, which would be around 50-65 deg C. How to calibrate? 1. Pick a diode current. This determines R_set 2. Determine midpoint voltage drop. Together with R_scale, this determines R_offset such that midpoint current through R_scale and R_offset cancel out. 3. R_gain can then be set independently Typical values: - 10k R/2R - 220 R_set (/ 1.7 220) 7mA - room temperature diode drop 400mV - R_scale 1K (initial guess) - (/ 1.7 0.4) 4.25 -> R_offset 4k7 - swing: (/ 1.7 0.2) -> 8.5 10k Entry: LVDS Date: Fri Oct 12 22:18:29 CEST 2018 http://www.ti.com/lit/ug/snla187/snla187.pdf Entry: FPGA Notes Axel Date: Fri Oct 19 11:45:07 CEST 2018 - CPU: split off fetch to break critical path, then use a delay slot for jumps - No don't cares in state machines, otherwise chip might not recover from getting into bad state due to power glitch or other electrical problem. - Also no tristate busses on ASIC: can't be formally verified that a bus is always driven. - Multiplexers are cheap on ASIC. Also on FPGA? Entry: Standard power input connectors Date: Wed Nov 28 09:38:38 EST 2018 What are those standard 2-prong and 3-prong connectors called? IEC 60320 Appliance couplers for household and similar general purposes https://en.wikipedia.org/wiki/IEC_60320 2-prong = C7 3-prong = C13 Reason for looking up: C13 daisy chain connectors. (Hosa makes some). Entry: Passive mixer Date: Wed Nov 28 21:34:57 EST 2018 10k into out node. EDIT: Wire the input if channel 4 as a mix of the other channels? I sketched it, and it seems the output will always have a mix of several channels. Maybe just get rid of the switching mechanism altogether. There is room inside the box for some other stuff. So, mod like this: - Mix all 4 channels using 10k into the output node. - Leave the switcher in there for some other functionality? EDIT: It's not worth it. Make a hard-wired thing. Not even necessary to use cables, just cut an RCA cable? Anyways, I should have enough. Entry: openwrt on tp-link HS-110 smart plug Date: Tue Dec 4 18:49:38 EST 2018 https://openwrt.org/toh/tp-link/hs110 https://www.edn.com/design/consumer/4458082/Teardown--A-Wi-Fi-smart-plug-for-home-automation Entry: Roku XD repurpose Date: Sat Dec 8 21:59:52 EST 2018 PNX8935E1/M101S1 Nexperia PNX8935E1 / M101S1 multi-format source decoder https://www.techrepublic.com/pictures/roku-xds-teardown/24/ https://www.smallnetbuilder.com/multimedia-voip/multimedia-voip-reviews/31284-roku-xds-reviewed?tmpl=component&print=1&layout=default&page= http://www.alldatasheet.com/view.jsp?Searchword=PNX8935E1 I don't find any actual sheets, but this is likely similar: PNX9520EN1 http://www.icpdf.com/PHILIPS_datasheet/PNX9520EN1_pdf_12974813/PNX9520EN1_3.html#view PNX15xx/952x based on TM3260 VLIW https://en.wikipedia.org/wiki/TriMedia_(mediaprocessor) https://www.linux-mips.org/wiki/PNX85XX PNX85XX - Nexperia umbrella name for ARM9, MIPS, Trimedia and EPIA DSP. - PNX8535 Digital One Chip of HDTV: MIPS 4KeC#240MHz + Trimedia DSP#290MHz + P89LPC9xx + EPIA Audio DSP, system software TV520/xx, MontaVista Linux based, GUI system Tara system Gmbh; - PNX8550 IPTV: MIPS 3K/4K? 200MHz + Trimedia DSP * 2 + P89LPC9xx, system software STB810, MotaVista Linux based, host system is Redhat/Fedura, GUI system DirectFB; - PNX8930 HD/IPTV/Hybird: MIPS 340MHz + Media Processing ASIC + P89LPC9xx, support both Linux and Windows CE 5. However Philips/NXP hesitate to support open source community because of the complex of Trimedia DSP and multi-core processing. Their current approach is selected ISV support Trimedia, and MIPS core keeps open for customer development. Seaching for "PNX8535 mips". MDS (Momentum Data Systems) provides support and dev board. ftp://tiger.satsale.net/tiger/!public_for_users/STB225/mds225_rev_1a.pdf md5://405edfaaa16aadefabfa577a67fc7a6a https://docplayer.net/36064627-Pnx8535-hybrid-television-processor.html MIPS + TM2270 Conclusion: not much can be done with this without A LOT of effort. Reuse as-is. However, I do wonder if there is a remote exploit for the older 2.6.24 Linux kernel. Some more useful hacking links: https://www.linuxquestions.org/questions/linux-networking-3/can-i-hack-into-a-roku-box-771797/ https://www.hackingnetflix.com/2008/07/roku-has-posted.html Entry: blackedge ECP5 FPGA board Date: Thu Dec 13 16:58:43 EST 2018 https://forum.mystorm.uk/t/the-blackedge-project/500 Entry: Sending nyquist signals over audio Date: Thu Feb 21 16:51:21 EST 2019 Basically, I want to send a keepalive signal that's inaudible so speakers can turn off when they don't see it. This as part of a single-wire (single-cable) setup for living room speaker. Also possible: use a balanced signal in a CAT5e cable for audio. Just an idea. Too much hassle wrt. power distribution. Entry: Volume control Date: Fri Feb 22 20:14:17 EST 2019 I had been thinking about an analog solution, but since it is already set up digitally and seems quite manageable, why not take one of those rotary encoders and hook it up to an STM32? This is more of a PIC thing maybe? Alternatively, do it analog so I can figure out how to do ADC. In any case, current midi controller would work fine. https://askubuntu.com/questions/97936/terminal-command-to-set-audio-volume pactl set-sink-volume 0 +10% Entry: Proximity detector Date: Mon Feb 25 14:17:41 EST 2019 I want something that can detect what terminal I'm at. Apart from something that is designed to do so, here is what I have: - keystrokes - motion detection Best would probably be some auth token. Entry: PCI and ISA breakout Date: Thu Mar 28 14:08:51 EDT 2019 Basically, I have these legacy PCI cards I'd like to hook up to a BBB. Probably someone thought about this before. Probably a better way is to look for a small form factor PC, and set up a Xenomai audio over ethernet bridge. EDIT: Yeah this is a bad idea. Avoid. Entry: Set up a synth work bench Date: Thu Apr 18 10:37:38 EDT 2019 So I think I'm clear what I need to do first to move the analog synth work from concept to reality: mod some existing circuitry, and bypass the power supply issue. Also, set things up permanently so it is easy to do this incrementally. Space is cleaned out. What's the first thing to work on? What's the first small step? Focus on creating the environment that can host small changes, increasing the reliability of the intermediate circuits. Maybe switch to dead bug style? Entry: Symmetric power supply Date: Thu Apr 18 11:56:14 EDT 2019 - mod existing synth circuits (fatman, monotron) - eurorack frame with 5V, +-12V - some pcb kit burried somewhere I have two with "green" banana sockets, though both have some issues. Entry: Wordclock BNC Date: Fri May 3 17:29:19 EDT 2019 https://en.wikipedia.org/wiki/Word_clock It measures 5V. Apparently 75Ohm. Entry: STM32F407 proto board Date: Tue May 21 13:26:05 EDT 2019 Black VET6 eBay board. Doesn't seem to respond to jtag. https://wiki.stm32duino.com/index.php?title=STM32F407#.22Black_VET6.22_STM32F407VET6_Variant The STLink on the discovery works: root@zoe:/etc/net/udev/openocd# openocd --command bindto 0.0.0.0 -f STM32_STLink_F4.cfg Open On-Chip Debugger 0.9.0 (2018-01-21-13:43) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html bindto name: (null) Info : auto-selecting first available session transport "hla_swd". To override use 'transport select '. Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD adapter speed: 2000 kHz adapter_nsrst_delay: 100 none separate Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : clock speed 1800 kHz Info : STLINK v2 JTAG v14 API v2 SWIM v0 VID 0x0483 PID 0x3748 Info : using stlink api v2 Info : Target voltage: 2.880000 Info : stm32f407vet6.cpu: hardware has 6 breakpoints, 4 watchpoints EDIT: Hold the board in reset, then it will connect. Likely as explained here: app likely has WFI in main loop, which stops clocking the core: http://nuttx.org/doku.php?id=wiki:howtos:jtag-debugging root@zoe:/etc/net/udev/openocd# openocd --command bindto 0.0.0.0 -f STM32_STLink_F4.cfg Open On-Chip Debugger 0.9.0 (2018-01-21-13:43) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html bindto name: (null) Info : auto-selecting first available session transport "hla_swd". To override use 'transport select '. Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD adapter speed: 2000 kHz adapter_nsrst_delay: 100 none separate Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : clock speed 1800 kHz Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748 Info : using stlink api v2 Info : Target voltage: 3.273307 Info : stm32f4x.cpu: hardware has 6 breakpoints, 4 watchpoints Info : accepting 'gdb' connection on tcp/3333 Info : device id = 0x100f6413 Info : flash size = 512kbytes undefined debug reason 7 - target needs reset Entry: stm prog Date: Sat Jun 15 20:44:27 CEST 2019 black gnd white 3v3 purple clock grey data set up both zni and tp to start a programmer, and also set up erlang on 29 to register the programmer. Entry: cisco isb6030 Date: Sat Jul 6 16:33:31 CEST 2019 https://www.circuitsonline.net/forum/view/141264 probably not so useful. box might be useful though. Entry: small boards Date: Sat Jul 20 10:25:45 EDT 2019 https://www.crowdsupply.com/groboards/giant-board Also points to: Onion Omega2 Pro https://onion.io/store/omega2-pro/ Entry: An RS485 bus Date: Sat Jul 20 13:13:18 EDT 2019 I've been thinking about this for a while. DMX might be a good fit since it can just go over balanced/stereo audio cables. EDIT: Seems a lot of issues with connectors and cabling as compared to just using USB. Not a good way to go. Entry: S/PDIF Date: Sat Jul 27 16:40:36 EDT 2019 http://www.hardwarebook.info/S/PDIF Entry: 3-phase motor, supercap Date: Wed Jul 31 23:44:15 EDT 2019 And have it be a "when there's power" computer. http://www.gohz.com/can-a-3-phase-motor-be-converted-into-generator-without-changing-its-speed Entry: RS485 sensor chain Date: Mon Aug 5 14:38:48 EDT 2019 I have plenty of cable, and plenty of STM32 nodes. So how to set this up? 12V, 5V, GND and a data pair. Is there a standard to send power directly over the other two pairs? https://pbxbook.com/other/rj45poe.html 802.3af Mode B (Midspan) delivers Inline Power on the unused pairs: 1 and 4, and therefore requires 4-pair cable. Midspan power supplies (external PoE injectors) provide inline power. But it's still 48V. Entry: "Scripts" Date: Mon Aug 5 18:01:19 EDT 2019 I need a way to quickly run something on an STM32F103 board. I don't even want to restart anything. Just from RAM. Simple things. I already have that, but let's build on it some more. Maybe it's better actually to prototype using rpi or bb, then move to buepill? No. Make it work on bluepill because those area really easy to have dedicated to a task. Entry: SD cards with LVDS connector Date: Sat Aug 10 13:37:48 EDT 2019 What's that called again? And how to get a phy chip for that? https://www.sdcard.org/developers/overview/low_voltage_signaling/index.html SD 6.0 I think I'm looking for UHS-II with the second row of connectors with 2 differential pairs and power. Entry: What is typical common mode an RS485 transceiver can take? Date: Sat Aug 10 14:15:44 EDT 2019 Can it be higher or lower than supply voltages? EIA says +- 7V on top of 0-5V supply voltages: https://en.wikipedia.org/wiki/RS-485#Common-mode Entry: DHT11 Date: Sun Aug 18 21:20:00 EDT 2019 It uses timed sequences. First let's make a notation. Each line starts at 1 and goes to transitions to end up at one. The numbers are the uS spacing. 18000 50 request 55 80 response 54 23 0 54 70 1 54 end Reply is 5 bytes. What is the simplest way to do this? Polling for transitions and timing them seems simplest. To make it low power, enable interrupts on the gpio and use WFI. STM32F103 has weak pullup pins, so let's give it a try. Really shouldn't be too hard. Entry: Single cable power and data Date: Sun Aug 18 21:36:17 EDT 2019 Every time I look at this, the simplest approach is to use CAT5 with two pairs for power, and two other pairs for data. Ring topology is simplest. Then send RS485 over these lines in the same point-to-point configuration. EDIT: Some more 2-wire solutions: http://e2e.ti.com/support/interface/f/138/t/75687 Entry: Can I get to 480MHz USB on iCE40? Date: Mon Aug 19 17:43:03 EDT 2019 Lattice says to use FT2232 https://www.latticesemi.com/en/Solutions/Solutions/SolutionsDetails01/EasyInterfacingtoUSB What is TinyFPGA BX doing? https://raw.githubusercontent.com/tinyfpga/TinyFPGA-B-Series/master/board/TinyFPGA-B.pdf USB P/N go straight in there. So that has to be 12MHz, i.e. no LVDS. https://discourse.tinyfpga.com/t/usb-communication/613 Entry: Audio Date: Mon Aug 19 22:34:51 EDT 2019 (* 3 8 96000) 2.3MByte/sec That is no problem on 100M This can even do two. So next project is a delta1010 board. Entry: data wants to be close to compute Date: Tue Aug 20 01:56:36 EDT 2019 https://www.anandtech.com/show/14750/hot-chips-31-analysis-inmemory-processing-by-upmem Entry: Bit-bang I2S Date: Tue Aug 20 17:54:24 EDT 2019 Is it actually possible to bit-bang this on a STM32F103? Entry: CML vs LVDS Date: Tue Aug 20 23:08:22 EDT 2019 https://www.cypress.com/file/74011/download Cypress AN1202 https://en.wikipedia.org/wiki/Current-mode_logic Entry: S/PDIF Date: Wed Aug 21 20:45:55 EDT 2019 bi-phase mark 3.0720 MBps >> factor(3072) ans = 2 2 2 2 2 2 2 2 2 2 3 3 * 1024 * 1000 http://www.hardwarebook.info/S/PDIF Entry: Modding iCE40-HX8K Breakout board Date: Sat Aug 24 08:00:12 EDT 2019 for uC boot. Basically I want control over the SPI bus + reset + CDONE, so I can have an STM32 boot this thing. Available: iCE_MISO J6.1 iCE_MOSI J6.4 iCE_SS_B J7.1 Needs patch wire: iCE_SCK U5.6 iCE_CDONE D10.1 iCE_CREST TP16 Entry: FT2232H to HX8K Date: Sat Aug 24 08:07:04 EDT 2019 FT2232H: Single channel synchronous FIFO mode for transfers upto 40 Mbytes/Sec Maybe it's time to just give that a try first. Is the HX8K board actually wired for FIFO mode? No. Entry: modifying D-link hub Date: Fri Sep 6 00:23:10 EDT 2019 Instead of relying on those cheapo hubs it might be a better idea to get used D-links. They seem to work well. Is the power pin accessible? Entry: two-wire RS485? Date: Mon Nov 4 11:22:57 EST 2019 I'd like to get rid of the ground reference to be able to use a single twisted pair for comms. Assume frequency is low enough such that termination is not an issue. Can a shared 2-wire bus be used as a 2-way bus? Unidirectional is simple. Bi-directional is not so easy as it requires the terminator resistor to be removed. It is very hard to compete with Ethernet. The only reasons to do so is to avoid a "hub device" at the far end. Any other solution with RS485 etc to avoid Ethernet is likely going to be more complicated. And once you have Ethernet, you will need an OS, which almost by default becomes Linux. So the reason to avoid ethernet is to keep the devices at the end of the cable simple. When does this make sense? When there are a lot of them, and when cabling can use hub-and-spokes model. Up to now the only thing I've used cheaply is Ethernet + USB. Entry: Using 100M phy in 10M mode on STM32F Date: Mon Nov 4 11:29:30 EST 2019 The clock will be the same, but data is "stretched", so this doesn't work out-of-the box without a clock frequency divider. Entry: Automatic RS485 shared bus interface Date: Sat Nov 9 11:02:42 EST 2019 Basically, it should follow the data and release whenever it has been high for a bit. It's ok to leave the line idle, you just need to drive it into its idle position such that resistors will just need to hold it instead of sourcing current to charge the cable. I've seen a cricuit for this before that used a cap to time the RS485 write enable release, together with a diode to charge when a 0 was written to the bus. DE is typically active high. What needs to happen? When the transmit line goes to 0, DE needs to go to 1 immediately, and the timeout is reset. When the transmid line goes to 1, DE needs to stay up for some time and then go low. Entry: dht11 over 2 wires Date: Tue Nov 12 12:43:23 EST 2019 - dht11 vcc is connected to cap - bus diode to vcc This is a lot of hassle because of >3.5V requirement. Use 3-strand. Entry: dht22 am2302 seems to work Date: Fri Nov 15 23:21:21 EST 2019 Accuracy to 0.1 rh and t Entry: i2s / spdif Date: Sun Nov 17 15:35:49 EST 2019 I'd like to build something isolated first, before wiring up the delta1010 boxes. How much more difficult is SPDIF? Because I already have that. I think the electrical is different. This uses a transformer for isolation: https://circuit-diagramz.com/coaxial-spdif-output/ For testing I can just use a resistor divider. 0.5V on 75 Ohm is 3.3V on 500 Ohm Entry: ecobee wiring Date: Mon Nov 18 18:03:28 EST 2019 Rc red Rh G green blue C Y1 yellow white W1 Y2 ACC- O/B ACC+ PEK Y1 is wired, but not enabled in the ecobee setup. This is the wire for cooling. My interpretation: Rc power W1 heating G fan C common https://xtronics.com/wiki/Thermostat_signals_and_wiring.html https://highperformancehvac.com/thermostat-wiring-colors-code/ To switch on: heat: Rh -> W cold: Rc -> Y fan: Rc -> G Entry: Delta1010 Date: Sun Jan 26 15:00:28 EST 2020 So I need to reverse this first. Document the drivers. This being 5V doesn't help so can I just solder into the box? Entry: a fun project Date: Mon Jan 27 14:11:17 EST 2020 Watching videos like this: https://www.youtube.com/watch?v=85ZCTuekjGA make my fingers itch. The Delta1010 is ambitious, and it is a "work" project. I also need a "fun" project. Basically, start making things that make analog noises. Doesn't really matter how, just a ball of mud is fine. Build it around the bluepill, and never remove anything. For the FatMan replacement, I will need a 5V interface. Chips are ordered. I think I'm not going to mess with PIC any more. So the fun projects all start with an exp converter. EDIT: Needs a bit more context switching than I thought. Entry: where does precision come from? Date: Mon Jan 27 15:13:29 EST 2020 precision: low frequency: use long time to measure high frequency: same (long time) but also count transitions so precision is basically time measurements + scale gets set by number of occurances. for frequency measurements, once it gets to high frequencies, the averaging isn't a problem. Entry: embedded RISC-V Date: Mon Jan 27 15:55:19 EST 2020 Basic idea: - use a bitserial RISC-V - QSPI program memory - standard C compiler https://github.com/olofk/serv https://www.librecores.org/olofk/serv How large is it? I guess I'm just going to have to try out fusesoc. 53 cores in @TrenzElectronic CYC1000 Cyclone 10 Sep 26 2019: New numbers are 228 FF and 294 LUT for iCE40 Entry: led board Date: Mon Jan 27 19:30:35 EST 2020 m12l16161a esmt sdram Entry: ws2811/ws2812 protocol Date: Sat Feb 1 05:02:46 EST 2020 1x0 382 ns 1 382 ns data 486 ns 0 1250 ns total per frame bit is sampled 588ns after 0->1 start bit edge (/ 1000.0 382) 2.61MHz (/ 1000.0 1250) 800kHz EDIT: Can this be run slower? Is there an actual datasheet? https://www.parallax.com/sites/default/files/downloads/28085-WS2812B-RGB-LED-Datasheet.pdf Since it is pwm, it might be simpler to actually use PWM. But then again it might be harder to get offsets right. Let's try SPI first. There is some slack += 150ns The code is high, low pulses. 0 = T0H, T0L 400, 800 1 = T1H, T1L 850, 450 RET = Treset > 50000ns (* 8 (/ 1000 72.0)) 111ns (* 16 (/ 1000 72.0)) 222ns (* 32 (/ 1000 72.0)) 444ns (* 8 111) 888 (* 8 222) 1776 STM32 sends back-to-back. It seems simplest to use one byte per bit. So question is: use DMA, which is memory inefficient, or use a state machine to compute the next byte? I already have DMA send working so let's use that for now. Then the question is how to split the bits. 3 bits, or 8? Using 3 bits allows using 72MHz / 32 which with bit time of 444ns Using 8 bits allows using word time of 1776 ns Let's try the simplest one first. EDIT: It works with SPI1 on DIV_16, then sending 0xC0 for a 0 bit and 0xFF for a 1 bit. EDIT: I can't get it to work with bitbang. 400ns is a bit too tight without a whole lot of effort. To do multiple of these, they could gated using 2 resistors + open drain pin per port. EDIT: Now make it work using only 3 bits? Entry: Amp Hour - Nash Reilly Date: Sun Feb 2 12:09:47 EST 2020 https://theamphour.com/474-an-interview-with-nash-reilly/ 1:01:50 H&W AOE: El Cheapo Special probe 10kOhm sig/gnd + RG174 50Ohm coax. 10kOhm : broad-band high impedance, isolating capacitance and inductance of cable. It's 12.2 in 3rd edition. Overlap with Howard Johnson Chapter 3 test & measurement, section 3.5.1 Shop-Built 21:1 Probe Entry: Ground loops Date: Sun Feb 2 14:13:22 EST 2020 https://www.edn.com/ground-loops/ Entry: Comp Arch lectures Date: Mon Feb 3 05:41:29 EST 2020 https://safari.ethz.ch/architecture/fall2019/doku.php?id=schedule Entry: Claire Wolf on the Amp Hour Date: Fri Feb 7 12:37:52 EST 2020 https://theamphour.com/374-an-interview-with-claire-nee-clifford-wolf/ Interesting history: designing custom processors on FPGA. Entry: kicad Date: Sat Feb 8 09:53:34 EST 2020 config is here: tom@roza:~$ rm -rf .config/kicad don't start eeschem directly, use kicad to launch it. apparently it does some magic. Entry: VGA timings Date: Sun Feb 9 22:04:14 EST 2020 http://martin.hinner.info/vga/timing.html Entry: logic optimisation complexity Date: Thu Feb 13 21:35:17 EST 2020 https://www.youtube.com/watch?v=WgBLHZkZm-E - 51:00 grows as 2^(2^n) - remark: so it seems to make sense that the form of initial specification does have some effect on the optimality of the outcome. - one way to simplify: write TT with don't cares - sometimes minimal circuits are not what you want: avoiding combinatorial glitches might be more important from a power and noise perspective. Entry: Colorlight mods Date: Sat Feb 22 10:41:35 EST 2020 https://twitter.com/Claude1079/status/1231194849350647808 Claude Schwarz @Claude1079 Received a bunch of SN74CBT3245APW 8bit bidirectional FET switches Those don't need a direction signal and are '245 pincompatible. Will mod my Colorlight 5A-75B with them, this should give true IO on every IO as bonus 5V tolerance on the IO with a little mod to the 5V rail. Entry: High Speed Amplifier Design Date: Sat Mar 7 15:00:18 EST 2020 This classic app note by Jim Williams is helpful for learning the practical side of high-speed design and breadboarding: https://www.analog.com/media/en/technical-documentation/application-notes/an47fa.pdf Entry: vbus sense hack Date: Sat Mar 7 16:52:32 EST 2020 Disconnect the 5V from the cable, and attach the vbus sense to 5V from the power supply through say 10k. Then connect that to a 5V tolerant pin on the stm32, and pull it down to turn off the hub. Entry: NPN transistor Date: Wed May 13 14:18:35 EDT 2020 I need to find something that can drive a small speaker. To limit things, let's pick a 100mA that is also at JLCPCB. 2N3904 1+ $0.198 200+ $0.0091 This can do 200mA I have a bunch of these already so let's stick with it. Entry: HC-SR04 Date: Wed May 13 21:55:42 EDT 2020 https://cdn.sparkfun.com/datasheets/Sensors/Proximity/HCSR04.pdf Send a 10uS pulse Entry: Next Date: Thu May 14 09:08:05 EDT 2020 - First test if dmx still works with all this stuff running. - Then LED patterns, sample upload, playback start/stop en implement control state machine. Entry: unbalanced to balanced (ground lift) Date: Fri May 15 23:28:32 EDT 2020 Does it make sense to connect a unbalanced output like this: T -- T S -- R S The S at the TS end is ground, but ti might be different than ground at the TRS send, so just send it to R instead to allow subtraction? Problem is that the impedance of the two is not the same... So what about adding extra impedance at one end, or just bridging it with a resistor? What is wrong with this picture? Entry: ws2812 noise / reflections Date: Sun May 17 01:00:14 EDT 2020 It was working, but only when scope was plugged in and with a 1k series resistor. This is what I got working now: over the line: 2n2 // 1k. Entry: How to learn to determine time constatns faster? Date: Sat May 23 13:49:49 EDT 2020 47p 22k To multiply these, keep in mind they are in a logarithmic range. 22 x 22 -> 470 22 x 47 -> 1000 47 x 47 -> 2200 Then, scales: pF * kOhm -> nS nF * kOhm -> uS uF * kOhm -> mS The frequency is 1 / 2 pi R C Maybe it's good to memorize a couple of tables. Start at a reference point around 20 200 2000 20000 (/ 1.0 (* 6.28 .0001)) (/ 1.0 6.28) (* 2 (sqrt 10)) Entry: good mosfet for 5V power rail switching Date: Sat May 23 19:06:11 EDT 2020 I want to use a 3v3 input to switch a pass transistor on a 5V power rail. What's a good go to part for that? This is driven by a STM32F103 so could also set up as a pulldown. Entry: SH11066 Date: Sat May 23 19:10:31 EDT 2020 https://www.ebay.com/itm/HiLetgo-1-3-SPI-128x64-SSH1106-OLED-LCD-Display-LCD-Module-for-Arduino-AVR-PIC/254424526577?ssPageName=STRK%3AMEBIDX%3AIT&_trksid=p2057872.m2749.l2649 Specifications: 1. Driver IC: SSH1106 2. Resolution: 128*64 3. Viewing angle: >160 4. OLED screens inside the driver chips: SSH1106. 5. Supports many control chip : fully compatible with Arduino 51 series,msp430 series , stm32/2 CSR IC , ETC 6. Ultra-low power consumption: full screen lit 7. Voltage: DC 3V-5V 8. Work temp : -30c-70c 9. Interface: SPI 10. Font Color: White SPI Pin definition: GND: Power ground VCC: Power CLK: Clock line MOSI: Data cable RES: Reset line DC: Data/commands CS: Chip select (when not use can be grounded directly) What is DC vs MOSI? Entry: dht22 calib Date: Thu May 28 23:26:29 EDT 2020 Marking them. I suspected the first one I used was off. Seems so. 1: at 87 2: at 78 That is quite a big difference. http://kandrsmith.org/RJS/Misc/Hygrometers/calib_dht22.html I put 1 back in. It started at 65. See if it is indeed hysteresis. No it jumps right past. Maybe try all of them? 1: 87 3: 78 4: 76 Ok one is bad. Entry: dht22 over one pair of wires? Date: Fri May 29 00:31:23 EDT 2020 A big enough cap should be able to do it, by switching off the 5V drive when communicating. It looks possible with STM due to 5V tolerant ports: - PNP switching 5V, driven by open drain gpio - diode + cap combo at DHT11 end Problem is charge current. 2N3906 is 200mA -> Rs=25 Ohm for 5V to limit charge spike. But power supply is probably the limit there. Probably more like 20mA or about 220 Ohm. EDIT: Can this be made symmetric? Not for voltage signalling, because you do need a ground return path for each of the +/- channels. Entry: Logic level Mosfets Date: Fri May 29 01:28:23 EDT 2020 What's a good default component here? These are the cheapest basic parts from JLCPCB: nMOS: 2N7002 7 Ohm at 5V pMOS: LBSS84LT1G 5 Ohm at 5V So this also needs to be driven from a pullup in a 5v / 3v3 circuit. Entry: Audio cables Date: Sun May 31 11:30:24 EDT 2020 Let's try to set up a networked system with audio cables. They are cheap, and are shielded, and should be able to get a 2-wire system going, feeding an stm32 at the other end. Entry: high side pnp switch Date: Sun May 31 18:44:48 EDT 2020 When driving from 3V3 without 5V tolerant pins, a low side transistor is necessary, together with a pullup resistor for the PNP to avoid it amplifying leak current. For 5V tolerant pins in open drain mode, there is no leakage current when open so just a base resistor is necessary. Entry: RS485-like current loop Date: Mon Jun 1 14:42:04 EDT 2020 Basically I want only two wires, and RS485 needs 3. So what if I terminate the end with a resistor acroos the pair and feed that into an rs485 reciever. The other end can then just be driven from gpio. For the application, only single ended communication is necessary. Or.. use an ethernet hub? It is probably possible to bit-bang 10mbit. I actually have a 10mbit switch. Actually I have plenty of opt-couplers. Why not just midi? EDIT: Here's a list - 10mbit bit-bang ethernet, transformer - simple current loop - load modulation - midi opto cupler - rs485 - rs485 current loop What are the disadvantages? - ethernet: needs proper frame generation, checksum, idle pulse. on STM32F this will have to be bit-banged using an instruction stream. - simple current loop: needs same ground - load modulation: needs some way to set base line. differentiating + schmitt trigger might be enough. - midi needs optocouplers at the receiving end - rs485 needs 3 wires + transceiver - rs485 current loop needs transceiver, but might be interesting to put to use those single ended transceivers. EDIT: While it's fun to think about, it really does not make any sense to do anything non-standard. I can come up with a million hacks, but nothing can beat ethernet backbone and USB fanout. Then when fanout length gets too long, use rs485. One thing that could be potentially useful is a rs485 backbone implemented with twisted pair. Use one pair for ground, one for 5V power. That leaves two pairs for data. This can even use one for 12V power to connect some routers as well. Entry: DHT11/DHT22 one wire Date: Mon Jun 1 21:31:07 EDT 2020 TL;DR Yes this works. 100uF cap across VCC and GND, diode from signal line to VCC. The cap is enough to survive the 20ms long message incurring a 400mV drop. This indicates the device consumes about 1.3mA in that period. Outside that time the device is still consuming power for 200ms, but we can drive the signal line to hard 5V as the dht11 will not pull it low. It appears to be charging through a pullup resistor internal to the dht11. --- Sensors are far apart, I'm going to need comms anyway, either between interface board and sensor, or between multiple sensor boards. Let's just try to turn DHT11 into a one wire sensor. Protocol needs to survive a 18ms pulse, so find a good cap/resistor value. Power consumption determines cap size. Resistor determines charge time and power consumption. Maybe best to use max value. DHT11 datasheet says 4.7k From 5.0V after diode drop we're at 4.3V. It needs 3.5V to operate. Probably best to just measure it. So this just needs to be tried. Currently it's using A0 but that is not 5V tolerant. I need to find a 5V tolerant pin and map it to an EXTI. Each of the 16 EXTI lines can select one of the ports. PA8-12 PB2 PB6-15 PC10-12 EDIT: The DHT11 needs a 470uF on 5V to survive a single cycle. It is in low power mode between things. The DHT22 seems to be continously on. So it seems that it might be necessary to keep it fed, turn off the feed transistor, do a transfer and turn it back on. EDIT: It does something for 200ms after communicating. If I keep the power stiff in that part the supply shouldn't dip much. The transistor can put out 200mA. I just want to limit the inrush, so that would be for 5V: 22 Ohm. With 22 Ohm, I can keep the cap at 100uF. There is a clear constant discharge during comms now, but the 22 Ohm resistor keeps the voltage constant during the 200ms communication and then ramps up again. 400mV over 30 ms on 100uF is? (/ (* 0.4 0.0001) 0.03) 1.3mA It is actually charging through that pullup resistor that is built into the device, which the DHT11 mentions is 4.7Ohm. So the series resistor can be removed. Now, is it possible to drive more than one circuit from the same power switch? It seems so. As long as they are all operated at the same time. Entry: 1-wire Date: Tue Jun 2 10:51:46 EDT 2020 This 1-wire trick would also work with other circuits. Just have to get a handle on the power consumption and proper comms sequencing. In the end it is about pulse timing and size of cap. Since they all have uuid, it's possible to use a hash of that id as time slot index. Entry: 5V power switch with mosfet Date: Sun Jun 28 11:27:58 EDT 2020 High side switch needs depletion mode. LBSS84LT1G I can't find anything in through-hole. PNP is probably ok. 2N3906 saturation voltage? 0.4V @50mA Ic Should be ok. Entry: Audio optocouplers Date: Thu Jul 2 17:55:12 EDT 2020 https://www.learnabout-electronics.org/Semiconductors/opto_53.php Entry: LM324 LM358 app note Date: Tue Jul 14 12:57:22 EDT 2020 TI - Application Design Guidelines for LM324/LM358 Devices https://www.ti.com/lit/an/sloa277/sloa277.pdf Entry: LM393 comparator Date: Wed Jul 22 20:21:21 EDT 2020 https://jlcpcb.com/parts/componentSearch?searchTxt=comparator 100+ $0.0359 https://www.onsemi.com/pub/Collateral/LM393-D.PDF also doesn't go up to Vcc.