A grab-bag of electronics circuits, theory recap, hacks and gear nostalgia. Before you trust what is in here, please note that my skills are most developed in the domains of software and general engineering/DSP math. My understanding of electronics theory is reasonably up-to-date, but from the practical design point I lack some experience. These lab notes mostly log the learning experience of designing some (analog) electronic circuits. See also notes about gEDA[1], notes about designing an analog synthesizer[2], ARM microcontroller development[3] and some digital electronics notes dispersed in the Staapl lab notes[4]. [1] entry://../geda [2] entry://../synth [3] entry://../arm [4] entry://../staapl Entry: Elektor Hacks: Symmetric voltages from MAX232 Date: Mon Sep 1 17:23:14 CEST 2008 From Elektor 2008-7/8 (uk version p.57): Gratis Symmetrical Opamp Supply Voltages[1]. This is interesting for analog/digital synth hybrid experiments, since most simple circuits really need a proper symmetric powersupply, and gives a standard serial port interface. Another interesting one on p.125: PR4401/02 off the Beaten Track [1] http://www.elektor.com/magazines/2008/july-047-august/gratis-symmetrical-opamp-supply-voltages.531321.lynkx [2] md5://9aa64ac57203684fd29ed398879fc3c8 Entry: Taking apart the Roland MC-303 Date: Wed Sep 3 16:35:06 CEST 2008 The idea is that I'd like to replace the motherboard with something else, turning the box into a controller, and turn the motherboard into a MIDI sound module. Let's see if the user interface can be cleanly separated from the main board. At first sight it does look like it: there are 2 separate PCBs for the top keyboard panel and the back panel with MIDI+AUDIO IO What follows is what I can figure out just looking at the board. Taking it apart: * remove back and bottom screws. leave the legs alone, they are attached to the bottom plate. * unscrew the mainboard (4 edges) * to remove the PANEL BOARD: disconnect 2 connectors so the mainboard and panel board can be unfolded. * remove knobs + gently pull off the big rotary knob, it is attached to the panel board. DON'T push the buttons with the panel board removed, since this will make the glue come off. also do not remove the dark screen, there's nothing there but glue. On the panel board I count 16 screws in total: 9 that attach to the chassis at the edge, and 7 that attach to a metal part that seems to be glued to the main chassis. Two of those are below the CPU board. Picture 1: Bottom plate removed, all connections intact. Picture 2-3: Jack Board unscrewed and exposed. Picture 4: Main board. JACK BOARD ---------- 74HC04AP hex invertor for midi PC910 optocoupler for midi 4 x C4570C NEC opamp 5218A dual low noise opamp pins con function ------------------ 4 CN5 5 CN6 volume knob (to PANEL BOARD CN3) 9 CN7 digital + power ? (to MOTHER BOARD CN1) PANEL BOARD ----------- 2 x 74HC138AP 3-to-8 Line Decoder 2 x TD62384AP 8CH LOW INPUT ACTIVE DARLINGTON SINK DRIVER 1 x TD62785P 8CH SOURCE DRIVERS 1 x 74HC245AP Octal bus tranceiver; 3-state pins con function ----------------- 5 CN3 volume knob (to JACK BOARD Cn6) 10 CN4 7x analog rotary knobs, 2 x GND, 1 x KNOB V+ (to MAIN BOARD CN2) 10 CN1 digital (to MAIN BOARD CN4) 12 CN2 digital (to MAIN BOARD CN3) Looks like most buttons have an associated LED. I don't see any load resistors though. Each switch has a diode in series. The source drivers are connected to the line decoders, and to the low end of the switches through a diode. The other end of the switch connects to a pull-up resistor and goes into the tristate. The tristate is also connecteded to the source drivers, which drive the leds into the sink drivers. service manual -------------- That's a lot more convenient: MC-303_SM.pdf from http://www.dtforum.net Looks like i missed the 22R resistors connected to the source drivers. Entry: Obtaining service manuals Date: Wed Sep 3 17:48:01 CEST 2008 http://www.dtforum.net They seem to have a good deal. $12 USD donation gets you one year access. Entry: CANbus Date: Wed Oct 8 02:13:29 CEST 2008 http://en.wikipedia.org/wiki/Canbus Intel i82527 CAN controller. Devices? http://www.testech-elect.com/peaksystem/pcan_pci.htm (82C251) SocketCan (CANbus as sockets: PF_CAN) contributed by VW research. http://en.wikipedia.org/wiki/Socketcan http://developer.berlios.de/projects/socketcan/ CANopen (CAN Festival) http://www.canfestival.org/ (also links to Xenomai) Now, since CAN is only upto 1mbit, why not run it over ethernet? Ether frame overhead (addresss + minimal length) shouldn't matter too much.. Entry: next microchip samples: Date: Sat Oct 18 15:51:33 CEST 2008 ENC28J60 ethernet MCP2552 canbus driver Entry: Legacy busses Date: Sat Oct 18 15:55:22 CEST 2008 ISA: http://upload.wikimedia.org/wikipedia/commons/0/0b/ISA_Bus_pins.png Idea is to get 8 x 1 bit / 1Mbps digital data into the PC. PIC at 40MHz is 10Mips, with one 8 bit port interfaced to an ISA 8bit register, this is probably really at the limit.. Can I use a PIC as an address decoder? For a dedicated PC, maybe it's possible to use a single address bit as chip select, and the remaining as function select? ATA (IDE): derivative of ISA PCMCIA: derivative of ATA COMPACT FLASH: derivative of PCMCIA ISA -> ATA? I didn't know that.. Maybe this can be used for PIC->PC data streaming, since the connectors are quite easy to use. What about PIO 0, 8,3 MB/S 8 bit? Entry: Weller WES51 Date: Fri Dec 26 15:26:32 CET 2008 Got one with 120V US powersupply.. Apparently, the transformer inside is not switchable: 120V/24V, 40VA. Bummer.. Entry: CANbus Date: Sat Jan 17 18:34:21 CET 2009 Electrical: LO HI allowed diff dominant 1.5 3.5 0.9 - 2.0 recessive 2.5 2.5 0.0 - 0.5 This is +-1V differential NRZ signalling. Main ideas of CAN: - communication in noisy environment - arbitration-free broadcast What about re-using networking cable + telephone wire? Local canbus: probably ok to use flatcable + shield? The idea is that CANbus does arbitration, so a local stackable bus on CANbus might be interesting. Does this still need a driver like MCP2551, or can the TX/RX lines be connected? As long as dominant/recessive is respected it should work just fine. Entry: Topcom UBR 624 (S3C2510A + IP175A) Date: Tue Jan 20 13:28:14 CET 2009 cosole IO: AF18 = CUTXD see library/pool/23C2510A.pdf also library/pool/IP175A\ LF-DS-R08-20060220.pdf For the serial port, there is a 2x3-pin header hole underneath one of the 1000uF capacitors, visible from the bottom of the board, with 2 traces running to the microcontroller. 1 GND 2 3 RX 4 TX 5 6 Connecting /dev/ttyUSB1,b19200,raw,echo=0 to - AT Firmware Version = R1.00b7 Command List: IP (set device IP; e.g. IP 192.168.123.254) PW (set new PassWord; e.g. PW admin) DS (toggle Dhcp Server setting) SR (Save new setting and Reboot) RR (Restore default setting and Reboot) SP (set memory address; e.g. SP80000000) OB (set one byte data; e.g. OB) IB (get one byte data; e.g. IB) OW (set two byte data; e.g. OW) IW (get two byte data; e.g. IW) OL (set two byte data; e.g. OL) IL (get two byte data; e.g. IL) RI (get interrupt mask; e.g. RI) SN (show nbuf; e.g. SN) Current Setting: Device IP = 192.168.1.1 DHCP Server = Enable > This[1] is the only google hit I could find, in Japanese. [1] http://pine.zero.ad.jp/meronsoft/mr_pbr007_01.htm Entry: EIA-485 Date: Thu Jan 22 09:45:06 CET 2009 The best solution is probably simple differential signalling over CAT5. This gives raw bit streams, so any protocol can be used (since we want a specific protocol anyway). It can be broken down the following way: - Ethernet/USB <-> EIA-485 : couples microcontroller to PC. - EIA-485 + power <-> TTL serial / SPI. What I really want is probably a linux/xenomai based ARM/POWERPC Ethernet <-> local microcontroller bus coupler. Entry: transceivers MAX3157 Date: Wed Feb 4 20:20:21 CET 2009 They are big. Wide 28-pins PDIP with a whopping 1309 transistors. uC lines: H /F half-full duplex selector TXP transmitter phase RXP receiver phase DE driver output enable DI driver input /RE receiver output enable RO receiver output Entry: profoon ip-22 Date: Mon Feb 16 21:04:29 CET 2009 SN11122APFR Probably related to SN11300 : 3 in 1 USB VoIP Controller http://www.sonix.com.tw/sonix/product.do?p=SN11300 Entry: CANbus over 2-pair telephone wire Date: Thu Apr 2 10:02:02 CEST 2009 2 pair power + CAN blue/purple GND/VCC white/green LO/HI http://www.interfacebus.com/Design_Connector_CAN.html 2 CAN_L white 7 CAN_H green 9 CAN_V+ purple 3 CAN_GND blue Entry: samsung 2333HD Date: Tue Apr 14 15:02:32 CEST 2009 service menu: POWEROFF 1 8 2 POWERON Entry: ninco dvx108 Date: Tue Apr 14 15:43:33 CEST 2009 sunplus 8202R board says: "GW-MPEG(8202R) V2.0 2007/10/18" Entry: Avnet Xilinx Spartan-3A FPGA board Date: Tue May 19 13:50:50 CEST 2009 While neuros system is compiling, let's have a look at the Spartan FPGA board. Board says: SPANSION Cypress PSoC Mixed Signal Arrays Spansion is the flash memory. The cypress PSoC is maybe a microcontroller for the touch pads? Yes, it's connected to CY8C24894-24L which has a PSoC programmer port on J2. PSoC programmer included in a separate package: Cypress CY3217 http://www.cypress.com/shop/?productid=287 The board has a url on the back side: http://www.em.avnet.com/spartan3a-evl Package contains: * Xilinx Spartan-3A evaluation board * ISE WebPACK 10.1 DVD * USB cable * Windows programming application * Now includes: Cypress MiniProg Programming Unit * Downloadable documentation and reference designs Key Features * Xilinx XC3S400A-4FTG256C Spartan-3A FPGA * Four LEDs * Four CapSense switches * I2C temperature sensor * Two 6-pin expansion headers * 20 x 2, 0.1-inch user I/O header * 32 Mb Spansion MirrorBit NOR GL Parallel Flash * 128 Mb Spansion MirrorBit SPI FL Serial Flash * USB-UART bridge * I2C port * SPI and BPI configuration * Xilinx JTAG interface * FPGA configuration via PSoC Supporting Products (BOM): Cypress Semiconductor CY8C24894-24LFXI Cypress PsOC Mixed-Signal Array Maxim MAX7381AXR166-T Maxim 3-pin Silicon Oscillator 16MHz Spansion S25FL128P0XNFI001 32 Mbit SPI Flash Memory Texas Instruments TMP100NA/250 TI Digital Temperature Sensor, I2C Interface TPS3809K33DBVT TI 3-pin Supply Voltage Supervisor, 2.93V Threshold TPS3106K33DBVR TI 3.3V Supply Voltage Supervisor TPS62290DRVT TI 1A Adjustable Step-Down DC-DC Converter SN74CB3T3257PW TI 4-bit 1 of 2 FET Mux/Demux Tpd=250pS SN74AHC1G08DBVR TI Single 2-Input and Gate forum: http://community.em.avnet.com/t5/Spartan-3A-Evaluation-Kit/bd-p/Spartan3A The download page: http://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D46501%2526CAT%253D0%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html?man=Xilinx Xilinx® Spartan®-3A Evaluation Kit App Notes/Ref Designs > Slave Serial Configuration from a Processor > Serial Flash (SPI) Configuration > Parallel Flash (BPI) Configuration ISE Design Suite 10.1 > MicroBlaze Design Introduction > MicroBlaze Parallel Flash Test and Execute in Place > ISE FPGA Design Introduction > MultiBoot in Serial and Parallel Flash > MicroBlaze Serial Flash Test > MicroBlaze IIC Temperature Sensor > MicroBlaze RTOS uC/OS-II Example BOM > Xilinx Spartan-3A Evaluation Kit - BOM Errata > Xilinx Spartan-3A Evaluation Kit - Errata Other > Restoring the Spartan-3A Evaluation Kit to Its Original State > Avnet Programming Utility Install for Windows XP SP3 > Avnet Programming Utility Install for Windowx XP SP2 and Vista > Master User Constraints File (UCF) > Avnet Programming Utility Reference Manual Design Kit Discussion Group > Xilinx Spartan-3A Evaluation Kit Schematics > Xilinx Spartan-3A Evaluation Kit - Schematics > Xilinx Spartan-3A Evaluation Kit - PCB Test Files > Default Serial Flash Factory Image > Factory Test Source Project (EDK 9.2) User Guide > Xilinx Spartan-3A Evaluation Kit - User Guide > Xilinx Spartan-3A Evaluation Kit - Quick Start Guide > Application Programmer Implementation Guide > Xilinx Spartan-3A Evaluation Kit - FAE Field Guide XBD > XBD Files (EDK 9.2i) > XBD Files (EDK 10.1 or later) some more stuff about the board: http://fpgablog.com/posts/avnet-cypress-cy3217-miniprog/ Entry: Atari 1040 STe Date: Mon Jun 8 00:18:58 CEST 2009 MC68901P Multifunction Peripheral MC6850P Async comm YM2149F Sound WD1772 Floppy controller MC68000 CPU MM9092 Blitter C300588 Video shifter LMC1992 Stereo tone and volume Anyways, It doesn't boot with the case on, but with the case removed it works just fine. I tried to exchange some disks with a linux PC without success, to try to get VolksForth[2] to work. Apparently there is now a project to simulate the floppy drive[3]. I closed the box and put it back into storage.. Can't do much with it except stare in awe ;) Apparently the wikipedia page[4] has a description of the chips. [1] http://www.memi.com/niko/studio/Gear/Atari/1040STe/ [2] http://volksforth.sourceforge.net/ [3] http://jeanfrancoisdelnero.free.fr/floppy_drive_emulator/index.html [4] http://en.wikipedia.org/wiki/Atari_ST Entry: Philips VG8020 Date: Mon Jun 8 01:16:11 CEST 2009 This was my first computer. I got a PC and got into C and x86 asm before I ever got serious about Z80 assembler. If I recall it was really hard to get good information. At one time there was a machine code monitor listed in one of the magazines my uncle subscribed to, which was my only source. I keyed it in but couldn't get it to work. A major disappontment which scarred me forever ;) I'd like to set that straight and get Staapl running on the MSX. To bootstrap it, the simplest way is probably the cassette interface: it's FSK to a maximum of 2400 baud. Should be quite easy to hook up to a PC or a simple uC circuit. The cassette tape input connects to the sound chip[3] through an interface circuit consisting of a single opamp configured as a schmitt-trigger. The cassette input is bit7 in register14 of the PSG. After bootstrapping with a standard "bload" format, this could be used directly to read other digital formats. Some more info here[4] and in the MSX Red Book[5]. [1] http://www.funet.fi/pub/msx/docs/service_manuals/philipsvg802000sm.pdf [2] http://msxbanzai.tni.nl/computers/philips.html [3] http://en.wikipedia.org/wiki/YM2149 [4] http://msx.retro8bits.com/msxtape.html [5] http://msx.retro8bits.com/msxarchives/aredbook.zip Entry: Charge pump Date: Wed Jun 10 17:04:22 CEST 2009 A charge pump[1] is a series of diode/capacitor circuits constructed like this: VDD --[>]--+--[>]--+--[>]--+--[>]--+--[>]--+--[>]--+ | | | | | | === C0 === C1 === C2 === C3 === C4 === C5 | | | | | | 1 2 1 2 1 2 It operates by switching the 1 and 2 nodes at opposite voltages. I.e. with 1=VDD and 2=GND, the 1 nodes supply a current that discharges the attached capacitor, goes through the diode and charges the next capactitor. This works as long as VC_i+VDD is larger than Vdiode+VC_i+1. Because this circuit is current controlled, connecting a voltage source to the nodes 1 and 2 will create a spike current. What I wonder is why one typically uses inductor-based boost convertors[4] for power supplies and not charge pumps. Maybe diode losses? I had this crazy idea of using the bounces of a switch to perform the initial transitions necessary to put a charge on a capacitor enough to bootstrap a microcontroller into driving the pump itself. Apparently the term "charge pump" is used also in PLL[3] circuits, which are used in voltage->frequency converters like [2]. This is where I encountered it today. [1] http://en.wikipedia.org/wiki/Charge_pump [2] http://www.national.com/mpf/LM/LM2917.html [3] http://en.wikipedia.org/wiki/Phase-locked_loop [4] http://en.wikipedia.org/wiki/Boost_converter Entry: booting msx Date: Mon Jun 22 02:02:27 CEST 2009 1. io ports 00-3F are available. this could be used to connect parallel interface to PIC. 2. how to boot? allow for memory mapped access + waitstates? [1] http://www.futurlec.com/Memory/28F010.shtml [2] http://www.futurlec.com/Memory/28F256.shtml [3] http://en.wikipedia.org/wiki/JEDEC_memory_standards Entry: simpleshare board Date: Fri Jul 10 15:55:55 CEST 2009 serial: 2x5 header[1]: pin 1 = logic high (3.3v) pin 2 = CTS pin 3 = Tx pin 4 = DSR pin 5 = RTS pin 6 = CD pin 7 = DTR pin 8 = RI pin 9 = Rx pin 10 = GND [1] http://openmss.org/forum/viewtopic.php?f=9&t=517 Connecting /dev/ttyUSB1,b115200,raw,echo=0 to - CFE version 1.2.14 for BCM94780 (32bit,SP,LE) Build Date: Tue Mar 15 13:14:24 PST 2005 (builder@nlab-sv1-builder) Copyright (C) 2000,2001,2002,2003 Broadcom Corporation. Initializing Arena. Initializing Devices. et0: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 et1: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 CPU type 0x29006: 264MHz Total memory: 0x2000000 bytes (32MB) Total memory used by CFE: 0x80300000 - 0x80442910 (1321232) Initialized Data: 0x8033CD30 - 0x8033F560 (10288) BSS Area: 0x8033F560 - 0x80340910 (5040) Local Heap: 0x80340910 - 0x80440910 (1048576) Stack Area: 0x80440910 - 0x80442910 (8192) Text (code) segment: 0x80300000 - 0x8033CD30 (249136) Boot area (physical): 0x00443000 - 0x00483000 Relocation Factor: I:00000000 - D:00000000 Device eth0: hwaddr 00-01-6C-BD-1E-1A, ipaddr 1.1.1.122, mask 255.255.255.0 gateway not set, nameserver not set Restoring NVRAM...done ÿ CFE version 1.2.14 for BCM94780 (32bit,SP,LE) Build Date: Tue Mar 15 13:14:24 PST 2005 (builder@nlab-sv1-builder) Copyright (C) 2000,2001,2002,2003 Broadcom Corporation. Initializing Arena. Initializing Devices. et0: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 et1: Broadcom BCM47xx 10/100 Mbps Ethernet Controller 3.60.13.0 CPU type 0x29006: 264MHz Total memory: 0x2000000 bytes (32MB) Total memory used by CFE: 0x80300000 - 0x80442910 (1321232) Initialized Data: 0x8033CD30 - 0x8033F560 (10288) BSS Area: 0x8033F560 - 0x80340910 (5040) Local Heap: 0x80340910 - 0x80440910 (1048576) Stack Area: 0x80440910 - 0x80442910 (8192) Text (code) segment: 0x80300000 - 0x8033CD30 (249136) Boot area (physical): 0x00443000 - 0x00483000 Relocation Factor: I:00000000 - D:00000000 Device eth0: hwaddr 00-01-6C-BD-1E-1A, ipaddr 1.1.1.122, mask 255.255.255.0 gateway not set, nameserver not set Waiting to load image on IP 1.1.1.122, ^C to abort...Failed.: Timeout occured Loader:raw Filesys:raw Dev:flash0.os File: Options:(null) Loading: .. 3732 bytes read Entry at 0x80001000 Closing network. Starting program at 0x80001000 Entry: Avnet Xilinx Spartan-3A FPGA board Date: Fri Jul 10 19:45:35 CEST 2009 So.. How to get this going. I copied the DVD to my HDD. It has version 10 of the tools. Ccurrently online it's 11, but quite a download so let's stick to the DVD. It includes software and evaluation versions of: - ISE Foundation - ISE WebPACK - ChipScope - PlanAhead - Platform Studio + EDK - System Generator for DSP and AccelDSP Synth Tool A description here[6]. Let's not bother with evaluation software and stick to things that are going to stay running. I suppose that would be WebPACK The tools need registration[1]. Registration ID: 1A9EAGT1TMJXSWSEXCZNG2360 Hmm.. Apparently the ISE WebPACK 10.1 doesn't run on 64bit, and in sid the ia32 stuff seems broken. Maybe 11.1 works with 64bit? Let's download it overnight. Next: quick start guide[2]. As far as I understand, the board is programmable through the PSoC over USB. I suppose the USB emulates a standard serial port. Are there any linux tools? Yes[3]. The Video[4] talks about SRAM + 16 multipliers on the Spartan-3A. What else does it have? Ok. Me like: apparently the board presents itself as an cdc_acm device. You can just get the interactive console using a terminal emulator. Ok. The linux utility can be found on google code[5]: svn checkout http://avs3a.googlecode.com/svn/trunk/ avs3a I use this wrapper script: [ -z "$1" ] && echo "usage: $0 " && exit 1 exec avs3a -s -p /dev/ttyACM0 -b $1 Now, the tools. I can start ise as Xilinx/11.1/ISE/bin/lin64/ise. It asks me what kind of project I'd like to start and I pick vhdl. Are there any examples to start from? It seems XST is the (command line [7]) synth tool. Next is maybe the ISE tutorial[8][11]. Chapter 2, HDL based design is what I want. Is it possible to bypass the IDE for now and go for straight VHDL -> bitfile? Also, there's a forum about the board[9]. A learning blog about this board[10]. Looks like the Xilinx tools use the Tcl language. [1] http://www.xilinx.com/register [2] https://www.em.avnet.com/common/poptxn/0,2741,RID%253D%2526CID%253D46501%2526CAT%253D0%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html?file=/files/177/s3aeval_quick_start_10_1_01.zip [3] http://www.nt7s.com/blog/2008/09/configuring-the-avnet-spartan-3a-eval-board-on-linux-alpha/ [4] http://www.youtube.com/watch?v=f1Mh8F0kVXE [5] http://avs3a.googlecode.com [6] http://www.xilinx.com/univ/dtools.htm [7] http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0032_6.html [8] http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise11tut.pdf [9] http://community.em.avnet.com/t5/Spartan-3A-Evaluation-Kit/bd-p/Spartan3A [10] http://blog.nirosoftware.com/ [11] http://www.xilinx.com/support/techsup/tutorials/tutorials10.htm Entry: Spartan-3A XC3S400A Date: Sat Jul 11 08:50:51 CEST 2009 Data sheet 3A family[1]. The FPGA is built out of 5 types of blocks: CLB (logic + FF), IOB, Block RAM, Multiplier Blocks, DCM (clock management). [1] http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Entry: I2C on PIC Date: Thu Jul 16 16:35:19 CEST 2009 Does it require external pullup? Is this maybe better to do anyway to make the setup symmetrical? [1] md5://1997353320958cc168dfb19e7e6a1a6d (4525) [2] http://en.wikipedia.org/wiki/I2c [3] http://www.robot-electronics.co.uk/htm/using_the_i2c_bus.htm Entry: FPGA vs. CPLD Date: Sun Sep 27 09:33:32 CEST 2009 Hugh Aguilar mentioned that for (Forth) processor implementation, CPLD might actually be better than FPGA. I'm not sure why though.. The only thing I found is that FPGA is better for applications that need a lot of registers. Entry: MyHDL Date: Fri Oct 2 13:25:36 CEST 2009 MyHDL[1] by Jan Decaluwe[2]. An LtU thread here[3]. An EE times article here[4]. A python-based HDL & modeling tool based on generators and decorators. In MyHDL, classic functions are used to model hardware modules. In particular, the parameter list is used to define the interface. Nested functions, generators and decorators should map cleanly to lambda abstractions, lightweight threads and mixins. I like the fact that generators are used instead of classes. This seems to be quite natural, as most OO-based dataflow code is centered around a 'process' method. Python generators are not generators in the traditional sense (they wrap just an instruction pointer, not a call stack), so a state-machine model is sufficient to implement them. This principle should be mappable to C code in a straight way generation of fast simulators. One of the more interesting aspects of MyHDL is the way in which conversion to Verilog is done[3]: The conversion does not start from source files, but from an instantiated design that has been elaborated by the Python interpreter. The converter uses the Python profiler to track the interpreter's operation and to infer the design structure and name spaces. It then selectively compiles pieces of source code for additional analysis and for conversion. This is done using the Python compiler package. [1] http://www.myhdl.org [2] http://www.jandecaluwe.com/ [3] http://lambda-the-ultimate.org/node/1258 [4] http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=177101584 Entry: VHDL Date: Fri Oct 2 15:03:43 CEST 2009 A tutorial[1]. [1] http://www.gmvhdl.com/VHDL.html Entry: Hints from Expert Date: Fri Mar 12 11:33:39 CET 2010 - use wide concave tip for soldering SMD: fix ends first. - dip wick in liquid flux before using to remove excess flux - use liquid flux with nail polish brush - solder 0805: put drop of solder on 1 end pad, solder one side first holding component with tweezers. - bga: he uses pick & place Entry: MSP430 in PDIP Date: Tue Aug 24 00:48:38 CEST 2010 Available in PDIP for the clumsy perfboard solderer. [1] http://www.embeddedrelated.com/groups/msp430/show/42099.php [2] http://www.ti.com/ww/en/mcu/valueline/index.shtml?DCMP=Value_Line&HQS=Other+BA+430value-promo [3] http://en.wikipedia.org/wiki/MSP430 [4] http://mspgcc.sourceforge.net/ [5] http://hackaday.com/2010/06/22/ti-makes-a-big-bid-for-the-hobby-market/ Entry: Creative use of SPDIF and 10Mbit Ethernet Date: Tue Nov 16 12:04:43 EST 2010 ( Bored with the serious stuff: pointless hacking time. ) I'd like to use the coax SPDIF on the Delta1010 to transform raw binary data to a PIC chip. How to proceed? For max SR of 96kHz we have 2x24 bit channels or 4.608 Mbit/sec. Same for ethernet? Problem there is probably generation of CRC checksums. [1] http://en.wikipedia.org/wiki/AES/EBU [2] http://en.wikipedia.org/wiki/Ethernet_frame Entry: Canon A540 firmware Date: Fri Nov 19 08:02:51 EST 2010 http://chdk.wikia.com/wiki/CHDK Canon PowerShot A540 P-ID:311B NT Firmware Ver GM1.00B E18 Jan 31 2006 11:02:45 Entry: Room acoustics Date: Sun Nov 21 11:21:08 EST 2010 I've got a 132 Hz resonance in the studio room. From the location of the zero (3/4 between the 2 corners) I think this is mode 2, with the root mode at 66 Hz. Indeed, at 66Hz there's a zero in the middle of the room. The corner-to-corner distance is about 4.5 - 5 meters. At 300m/sec this gives: (/ 300 5) -> 60Hz The distance is then probably more like 4.5 meters: (/ 300 4.5) -> 66Hz Edit: some more measurements. 132Hz is a 2.2 meter wavelength, which is 1/2 the distance between the cross corners. Maybe put a bass trap in one of the corners. [1] http://www.gearslutz.com/board/bass-traps-acoustic-panels-foam-etc/347485-130-hz-peak.html Entry: RC segments Date: Tue Nov 23 18:11:29 EST 2010 Type: tex {\tiny Part of an attempt to revive analog circuit intuition. } Observe the low--pass filter in [1] right before the input of the delay line. It contains 3 sections with a time constant of $22$us, $45$kHz when they would be in isolation. However, they are coupled with the next stages loading the previous. This is why the restor/capacitor ratio shifts: each stage $R/C$ goes times $10$ with $RC=\tau$ constant. Assume the 3 sections are isolated (i.e. there is a unit gain buffer between the RC sections), and assume their time constants are the same. At $f = 1/\tau$, the $3$dB point, the magnitude of the impedance of each capacitor is equal to that of its resistor, though with a $-j = e^{-\pi/2}$ phase shift. The first section's capacitor is then at $-10j$kOhm, while the second is at $-33j$kOhm and the third is at $-100j$kOhm. The point is now that with the buffers removed, and each section loading the previous, the time constants won't shift that much because the loading impedance is quite a bit larger than the capacitor impedance. I.e. $10$ kOhm vs. $33-j33$ kOhm Calculating the transfer function by hand is a bit tedious. Might be best to writ a small program to see how the poles split in terms of the $R/C$ ratio increment per stage. Another approach is to write a form for the infinite chain, and tap it at some point: $$Z_n = \alpha^n R + ( j\omega C a^{-n} + Z_{n+1} ) ^{-1}$$ % [1] http://www.uni-bonn.de/~uzs159/pt2399.html Entry: Printing from OSX 10.5 to cups on linux Date: Sat Nov 27 13:00:41 EST 2010 Pff.. Why do they have to keep changing everything all the time? I used to be able to just add a queue using the CUPS web interface but now it's hidden behind menues, and I get faulty output. Maybe use LPD instead of IPP? Entry: Bass guitar noise pickup Date: Tue Nov 30 19:20:07 EST 2010 I notice a big difference between plugging the bass straight into the Behringer UB1202 or first into one of the pedals: Behringer OD300 or Danelectro FAB Echo. The difference is probably that the UB1202 has a 10k input impedance, and the pedals use a much higher value. Measuring the resistance using a multimeter gives either open circuit or negative resistance. Why is that? Maybe base current from bipolar input stage. It seems that the XLR inputs are 2k6 balanced, while the TRS inputs are 20k balanced. What's the output impedance of the bass? It measures 10k (guitar measures 5k). Then I wonder why all guitar effect schematics I find online have such high input impedances. This seems to significantly increase hum pickup. Going further I found this[1] discussion about pickup impedance. So, the whole story goes like this: a linear transducer can be modeled as a voltage source with series resistor (Thevenin equivalent) or a current source with parallel resistance (Norton equivalent). The question is how to load it. There are 3 extremal points in the load impedance: - high: z_in >> z_out, i.e z_in = infinity: max voltage - low: z_in << z_out, i.e. z_in = zero: max current - matched: z_in == z_out: max energy So I wonder: what about loading with z_in = 0 and measuring current only? [1] http://www.diyaudio.com/forums/musical-instruments/33294-low-impedance-pickups.html Entry: Guitar pickups cont.. Date: Thu Dec 2 00:07:49 EST 2010 What I read online is that a typical pickup has an inductance of 4H. This hits 10k at f = 400 Hz. So the loading should significantly alter the sound. See also measurements here[1]. What I didn't know is that the cable makes such a difference, as the cable capacitance is significant in the RLC chain and can shift the reso freq. [1] http://buildyourguitar.com/resources/lemme/ [1] http://www.geofex.com/effxfaq/distn101.htm Entry: Audio card scope Date: Fri Dec 10 16:12:00 EST 2010 I tried both xoscope and qoscc. First one only uses /dev/dsp which doesn't work for me (unless I have emu jack->dsp) and the second one is way too slow and also seems to be quite buggy. So, let's dig up pdp_scope~ again. At least that will give some control. What I need is: - Triggering - Autoscaling (time and amplitude) - Grids - A pretty display (bresenham / virtual phosphor) Triggering can be best added to creb, as it seems universally useful, also for dynwav. Maybe there is already something like it? Alternatively: use delay lines. They are already part of pd and have exactly what is needed: a variable window into the past. EDIT: wrote a new one[1]. [1] http://zwizwa.be/darcs/scope Entry: Scopes Date: Fri Dec 10 19:10:39 EST 2010 I found the one I have in Belgium on ebay[1]. G72515 Goldstar OS-9020A 2-Ch Oscilloscope 20MHz Finally bought this one[2]. Leader LBO-526 60MHz 2-Channel Dual-Trace Oscilloscope [1] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=330506857430 [2] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=380297166598 Entry: DI box Date: Sun Dec 12 00:51:34 EST 2010 What I need: - 2 inputs - mix (crossfade) knob, or 2 gain knobs. - multi out (+ possibly send level) Entry: Induction motor generator Date: Wed Dec 15 23:02:03 EST 2010 The key to bootstrapping is the residual magnetism in the rotor. Questions: - Where to get low-power, low-rpm motors? - For illustration purpose: how to build 3-phase induction motor from scratch? - Is there a relation between AC freq, RPM and bulkyness? To summarize: 1hp is 750W. [3] claims peak power of 300W. So a 1/2 to 1 hp motor should be enough. [1] http://www.youtube.com/watch?v=ADRK_NkQ-eU [2] http://www.qsl.net/ns8o/Induction_Generator.html [3] http://www.econvergence.net/electro.htm [4] http://www.pedalpowergenerator.com/#FREE Entry: LED lamp controller Date: Thu Dec 16 00:44:50 EST 2010 Got a cheap LED lamp[2]. However, this doesn't seem to work too well from 1.2V rechargables as the voltage drops fast. The LEDs are at 3.5V and the regulator is a 1Ohm resistor. A nice excuse to build a circuit. For a buck-boost converter[1] the LED can be used directly as the switching diode. The only problem is how to measure the current. I don't have low-ohm resistors in stock. It might also be possible to let the LED go out such that voltage feedback can be used. If switched fast enough we won't notice. Depending on the known value of the inductor we can use pulse width timing to charge it up to a certain max current, then let it discharge fully in the LED. When the current goes to zero, the voltage suddenly drops which can initiate a new charge cycle. Problem with buck-boost in [1] is the negative voltage. I.e. using a simple PNP switch, the emittor will be pulled down by the inductor whenever the current is switched off, so the base needs to be tied to the emittor through a resistor. Then switching the base from Vcc/High-Z should work. Problem is that the High-Z voltage on the PIC pin will be the negative inductor voltage, so the protection diode kicks in turning the transistor on again.. Not so simple! Solution might be to add an extra diode, though then the problem is to make it conduct in the first place. Need to read more.. Found this[4]. A different topology though. Starting from such a topology and doodling a bit it seems it's quite simple if the LED can go out during the inductor charge cycle. I arrived at two conclusions: - The buck-boost in [1] needs a PNP transistor switch. (duh!) That way the coil end is at a the collector, and it can go negative without any problems. - Starting from that PNP schematic, it can be inverted by changing battery polarity and using a NPN switch. For 2.2 mH (what I ordered) and a 5V supply it will take 130us to charge the inductor to 300mA. Discharging it through 3.6V will take about 180us. It seems that this really doesn't need a closed loop controller as long as the inductor is fully discharged during the transistor off time. Measuring the voltage across the LED is going to cost two resistors. Then it seems simpler to just use one low-ohm resistor on the transistor emitter to measure the inductor current directly. [1] http://en.wikipedia.org/wiki/Buck%E2%80%93boost_converter [2] http://www.amazon.com/gp/product/B001F1UFR6 [3] http://www.edn-europe.com/buckboostconverterschangewiththetimes+article+2201+Europe.html [4] http://www.digchip.com/application-notes/3/12977.php Entry: Tayda: staple transistor 2n3904 / 2n3906 Date: Thu Dec 16 20:13:25 EST 2010 Cheaper transistor at Tayda: 2n3904 NPN $1.9 http://www.fairchildsemi.com/ds/2N/2N3904.pdf 2n3906 PNP $2.9 http://www.fairchildsemi.com/ds/2N/2N3906.pdf The BC559 / BC549 from Futurlec are $0.08 each. Entry: Using CMOS inverters as linear amplifiers Date: Fri Dec 17 00:11:32 EST 2010 With proper biasing, the s-curve inverter amplitude transfer function can be exploited for smooth distortion. I was thinking about moving this one step further and implement SVFs. TAOE's section on the CMOS inverter mentions the use of CMOS inverters as cheap open loop amplifiers when the waveforms aren't important. It mentions a biasing network with a shunting capacitor that's open loop for AC. This also appears in [3] ("treble boost"). The app note[2] mentions linear (feedback) applications. Questions: - How much current does a 1/2 biased inverter draw? - Can we feed the inverter with a current source to control gain? How are g_m, gain, current and voltage->current related? One strange thing about [2] is that DC gain _drops_ when voltage rises. - How to bias a-symmetrically? Bottom line: * A CMOS invertor behaves mostly like a low-gain opamp with non-inverting input tied to +- 1/2 Vcc. * For distortion, we're interested in the open-loop gain. [1] md5://4547016f823d5ad574cf77c44608409d [2] http://www.qsl.net/l/lu7did//docs/QRPp/TTL_CMOS%20As%20Linear%20Amplifier_AN-88.pdf [3] http://www.aronnelson.com/gallery/main.php/v/WGTP/Red+Rooster.GIF.html?g2_imageViewsIndex=1 Entry: Resistor color code mnemonic Date: Sun Dec 19 21:28:49 EST 2010 Bad beer rots our young guts but vodka goes well – get some now The colors are sorted in the order of the visible light spectrum: red (2), orange (3), yellow (4), green (5), blue (6), violet (7). Black (0) has no energy, brown (1) has a little more, white (9) has everything and grey (8) is like white, but less intense.[8] [1] http://en.wikipedia.org/wiki/Electronic_color_code#Mnemonics Entry: Capacitors and resistors: getting a feel for component values Date: Wed Dec 22 17:01:23 EST 2010 Managing Impedance ------------------ One of the essential elements of good circuit design is to manage the orders of magnitude -- to optimize circuit impedance. Most designs allow to be run at higher current/voltage which is good for noise immunity but bad for component cost (bigger size) and operating cost (larger power cost, heat production). I remember this to be one of the earliest discouraging problems I ran into, trying to obtain expensive large Polypropylene capacitors for a filter circuit I designed on paper because the resistors values I used where on the small side. In those days I had nobody to turn to and no access to information that was in a form I could digest, so I gave up. In recent years and especially the last couple of weeks getting my hands dirty and reading schematics, these things have become more clear to me. So, as an illustration, here's a problem I ran into which hints at the "muscle memory" you need to create about resistor and capacitor values. Dynamic range ------------- The problem is that both resistors and caps have a large dynamic range of useful values -- about 8 decades each. - 0.1 (10^-1) -> 10M (10^7): - 1000u (10^-3) -> 10p (10^-11) As a result the time constants that come from combining these have about 15 decades. That's a pretty large time scale from 11 days to 1 picosecond (1 teraHz). The time scales for audio processing are luckily a bit less large, about 3 decades from 20Hz to 20kHz, or 4 from 5-50kHz depending on how you count. However, due to the large range of R and C, there are about 10 - 11 decades of impedance to choose from when RC time constants are given. That's quite a lot. Most of this is ruled out as either too high (instrumentation amplifier) or too low (power amp), which leaves a good 3-4 decades where resistors range from 220Ohm to 2M. The Art of Electronics[1] (p. 279) has a rule of thumb that that says to pick a capacitor value in based of 10uF / Hz. This places resistor values around 10-20k. It doesn't really explain why. At another point ([1] p. 275) it mentions to pick resistor values in the 10k-100k range, as lower values tend to get closer to the open loop impedance of opamps as frequencies rise. My guess is that higher resitor values are to be avoided because of noise. (TODO: add some quantitative explanation here). The problem ----------- Currently I have only 50k dual log (A-type) potentiometers I want to use in a SVF filter. The lowest frequency of interest is 20Hz, which brings the capacitor value to about 160nF, which rounds down (frequency) to 220nF. That seems rather large for a ceramic cap. The largest I have here is 100nF, and it's a ceramic multilayer (the microphonic ones). The smallest ceramic disc cap I have is 47nF (473). Let's check some Futurlec[2] prices to see where they start to rise significantly. Capacitance Max Smaller Price Largest Type ----------------------------------------------------------------------- 100nF 2200nF $0.07 $0.12 $0.60 100V Mylar 150nF 2200nF $0.06 $0.15 $0.30 50V Multilayer Ceramic 100nF 100nF $0.05 $0.10 $0.10 50V Ceramic Disc That looks like a trend. From the cost perspective it seems to be a good idea to keep capacitors below 100nF, which means impedances should be 100k or above for to get to RC frequencies below 20Hz. Conclusions ----------- For full audio range SVF time constant setting, use a 220n cap if 50k is given, but if possible, raise the POT to 500k and use a 22n cap. EDIT: For SVF, the loop gain can be lowered to end up with smaller cap values for the same frequency range. [1] isbn://0521370957 [2] http://www.futurlec.com/Capacitors.shtml Entry: CPLD Date: Sat Dec 25 12:23:37 EST 2010 The Atmel ATF20V8B[1] seems like an interesting part to play with. I found it looking for PDIP CPLD. [1] http://www.atmel.com/dyn/products/product_card.asp?part_id=2084 Entry: Weird brain fart: open vs. closed loop bode plots Date: Sun Dec 26 11:56:12 EST 2010 Context: state variable filter. If 2 integrators produce 180 degree phase shift, why does the circuit oscillate where loop gain = 1, and not where gain is larger? Very bad formulation and I don't know if I can fix that, but the idea is this: don't confuse time domain behaviour with s-parameter model. If the frequency is well below 1/tau the integrators are "fast enough" and will follow the input signal. Entry: Pedal power Date: Tue Dec 28 22:11:25 EST 2010 1. Brushless. Without a doubt. Both for aging and efficiency. 2. Induction motor + some way to bootstrap it in case it is not magnetized, i.e. smaller synchronous motor. 3. Battery / supercaps. Some form of storage is necessary. Lead-acid doesn't work indoors. Can it be made with minimal storage? I.e. keep the energy mostly in "human" form, but allow for catching breath and changing operators. Entry: Generator from 1-phase motor Date: Wed Dec 29 22:48:42 EST 2010 MOTOR A 1-phase induction motor motor is actually a 2-phase motor, with a capacitor providing the +- 90 degree phase shift. Is it possible to ditch the cap and use it in proper 2-phase? I.e. is the 2nd phase somehow cripled for power rating? Context: low-power 3-phase motors are expensive. Low power 1-phase are almost free (old junk). It migt be more interesting to concentrate on recycling junk to build crank generators. However, a 3-phase is supposed to be more efficient[1]. Why is that? Is it true that a 1-phase motor does not give constant power? This makes sense, as both V and I go through zero at the same time (ignoring coil inductance). ELECTRONICS For low rating (+- 100 W) the electronics are also going to be a lot cheaper. Where to get transistors? [1] http://users.telenet.be/b0y/ Entry: Staapl nudge app: LED driver Date: Thu Dec 30 16:01:30 EST 2010 What should be the app driver for cleaning Staapl up to a usable s-expression level? What about an LED boost converter? Entry: BEAM robotics Date: Fri Jan 14 22:54:17 EST 2011 KISS analog control. [1] http://en.wikipedia.org/wiki/BEAM_robotics Entry: Breadboarding Date: Sun Jan 16 19:04:22 EST 2011 I've been looking into some straightforward way to make prototypes. What I want to do is very simple: analog circuits with a lot of discrete components. However, I feel I loose too much time on building and debugging bad solder joints. Options: * I've been using pad-per-hole perfboard for a while. I like it better than stripboard because it's possible to design a fairly compact 1-sided PCB with fat tracks and copy it using component leads. * Home-made etched PCBs. It seems that most options are quite a lot of work. Toner transfer, etching, drilling. * Home made milled PCBs. Requires some equipement. * Fabbed PCBs. Either expensive, or long lead time. * Wire wrap. I'm gathering some tools to try it out, but it seems expensive too. * Combination soldering / wire wrap. Might be best for what I want to do, but need to try first. One thing I ran into though is the over/under rule for wire wrapping. See[1] : Put in all your level 1 to level 1 wires first, then the level 2 to level 2. The only level 2 to level 1 wire should be at the end of a chain. If you follow this rule, you never have to take off more than 3 wires to make a change. I wonder if this approach makes sense for pad-per-hole breadboarding too: don't worry about component placement or bending wires, just construct all nets as chains with max 2 connections per component pin. [1] http://www.fliptronics.com/tip0003.html Entry: 1/f noise Date: Mon Jan 17 11:28:59 EST 2011 I read recently that the 1/f noise in amplifiers is essentially not bounded from below in frequency, meaning it can become very problematic for true (non-leaky) integrators. I don't know the exact context of this, but that seems like a strange phenomenon. What is this about? [1] http://en.wikipedia.org/wiki/Flicker_noise Entry: Translinear Principle Date: Tue Jan 18 23:25:09 EST 2011 I can't remember running into the Translinear Principle (TLP) before[1], especially not in school. ( Of course I did run into log/antilog converters and current mirrors. ) The TLP is a product rule for currents through translinear elements (TE). To simplify, a TE is a forward biased PN junction, i.e. a diode or BJT BE junction. It's quite nifty: * Construct a loop that goes through TEs traversing each element forward or backward. A loop needs to contain an equal amount of TEs traversed in the 2 opposite directions: clockwise (CW) and counter clockwise (CCW). * By Kirchoff's law, the sum of all the forward voltages of CC TEs equals the sum of all the forward voltages of the CCW TEs. * By the exponential V->I law, this implies that the product of the forward currents through all the CC TEs equals the product of all the forward currents through all the CCW TEs. [1] http://en.wikipedia.org/wiki/Translinear_circuit Entry: Opening up FV6020 Date: Thu Feb 3 19:24:14 EST 2011 Let's look inside. SOC: Infineon PSB 21553 E V1.4 INCA-IP-S RAM: SAMSUNG 434 K4S641632H-TC75 FLASH: 29LV160 TP7 on the board has the serial console. It's the first time I followed a point and shoot approach. 1. Identify ground to connect to scope probe ground. 2. While booting, identify which pins are high: they are either idle serial, or VCC. 3. The TX line will clearly show signal. The other one is VCC. 4. Identifiy ground by measuring resistance to the known ground connector. 5. Look on the board: 2 traces run to the SOC, this is RX and TX, so that identifies RX and confirms TX. TP7 TX . . RX . . 3V . . GND Baud rate is 115200: Attaching interface lo0...done error column the TSF reg is 0x2 Starting at 0x80010000... VLAN_CTRL: PC LAN CPU send only to Members: + - - accept untagged packets: + + + VLAN aware: NO VLAN_CTRL: PC LAN CPU send only to Members: + + - accept untagged packets: + + + VLAN aware: NO VLAN_CTRL: PC LAN CPU send only to Members: + + + accept untagged packets: + + - VLAN aware: NO Port VLAN ID PRIO PC : 0x0001 ( 1) 0 Port VLAN ID PRIO LAN : 0x0002 ( 2) 0 VLAN table entry added: index = 0, VLAN ID = 1 (1), Ctrl = 65 VLAN table entry added: index = 1, VLAN ID = 2 (2), Ctrl = 66 VLAN_CTRL: PC LAN CPU send only to Members: + + + accept untagged packets: + + - VLAN aware: YES ----->equal++sw0x 807ffe00 (8041e760tRootT ask------>inaterface name ): swVSW END LOAD unit 0x0807f fe00 (tRootTask): VSW END LOAD Attached TCP/IP interface to sw unit 0 Attaching interface lo0...done Adding 9123 symbols for standalone. VxWorks Copyright 1984-2002 Wind River Systems, Inc. CPU: INCA-IP BSP Runtime Name: VxWorks Runtime Version: 5.5.1 BSP version: 21553.1.0.1 1.14.0.3 Created: Jan 17 2007, 10:27:33 WDB Comm Type: WDB_COMM_NETWORK WDB: Ready. -> Read configuration from flash ..............................Finished Initializing the DSP module 0x806f4950 (tGwStart): msqDTMF is generated,code is 0x806de9b0 Download successful! 0x806f4950 (tGwStart): msqDTMF is delete,code is 0x0 0x806f4950 (tGwStart): msqDTMF is generated,code is 0x806de9b0 ..............................Finished Start up network module ..............................Finished Start up SIP module ..............................Finished Start up IAX2 module ..............................Finished Start up call manager module ..............................Finished Start up config mangement system..............................Finished uiCallInform:0,0 started, version 2.0rc1 cachesize 150 Login: [MGR] | NOTICE |DHCP client start OK [MGR] | INFO |DHCP Server Start Success [MGR] | NOTICE |NAT module Start Successfully [SIP] | WARNING|info: Starting osip stack and osipua layer. [SIP] | ERROR |info: port already listened [SIP] | NOTICE |allocating transaction ressource 1 841012261-270525659 [SIP] | NOTICE |allocating NICT context [SIP] | WARNING|info: Entering osipua thread. [MGR] | INFO |>chan 0 is handed up,status:0 uiCallInform:3,0 Entry: Interfacing 3V3 and 5V applications. Date: Fri Feb 4 13:16:18 EST 2011 From [2]: "There are many ICs available on the market that are specifically designed to translate between logic levels. We've never used any of them!" The basic ideas are: * 5V -> 3V: use a current limiting resistor. This requires the 3V3 input to be protected with clamping diode the 3V power supply! * 3V -> 5V: no resistor necessary, inputs are compatible. I guess it doesn't hurt to place one anyway in case master/slave roles are reversed? SPI bus with the 5V device as master, as seen in the example in [2]: * MISO: master input slave output (3V) * MOSI: master output slave input (5V) * SCK: master clock (5V) [1] http://www.nxp.com/documents/application_note/AN240.pdf [2] http://www.sparkfun.com/tutorials/65 Entry: 3.3V from different regulator Date: Sat Feb 5 09:50:00 EST 2011 I have a bunch of regulators, but no 3.3V ones. If I recall there is a trick to get a different voltage from a linear regulator by changing the feedback path.. How did that go? See data sheet [1]. That only shows how to raise the voltage though. This seems to be the default configuration for a component like [2] which has a 1.25V reference. The ARM board uses the L4931C33[3]. What about using a red LED to take the voltage drop/ That should be about 1.8V? ( Measured: the bright reds I have here are 1.67V which is pretty close to perfect. ) So from 5V we go through the led to a buffer cap. Placing a resistor parallel to the buffer cap should prevent the LED to turn off, which would lower its voltage, ultimately charging the cap to 5V if there is no load attached. Hmm.. There's another problem: 5V across the LED when cap is not charged, so this would need a current limiting resistor also. But if the input also has a cap, that problem is solved. Seems quite a hack.. Ha, I found somebody suggesting it here[4]. Anyways. I placed an order at Tayda. Maybe visit RadioShack for some 3V3 regulators. Other than that, I do have all components to solve my most basic need. [1] http://www.futurlec.com/Linear/78L05.shtml [2] http://www.national.com/mpf/LM/LM317.html#Overview [3] http://www.st.com/internet/analog/product/63164.jsp [4] http://www.electro-tech-online.com/general-electronics-chat/88621-convert-5v-dc-3-3v-dc.html [5] http://www.4uconnector.com/online/itemagrid.asp?seriesdesp=2.54+FEMALE+HEADER+PLUS+TWO+BASE+DIP+STRAIGHT+HEIGHT%3D13.59MM&seriesno=0197&GroupNo=01&groupdesp=Pin+%2F+Female+Header&itemnum=5324&sample=&seriesnum=96& Entry: SPI basics Date: Sat Feb 5 12:16:23 EST 2011 The SPI bus is a point-to-point connection with one master and one slave. The master generates the clock. There are 4 signal lines: MISO: master input slave output MOSI: master output slave input SCK: master clock SS: slave select (CS: chip select) The MISO/MOSI naming connects pins with same names. An alternative naming scheme: SDO: serial data out SDI: serial data in names pins according to data direction. This requires SDO<->SDI connections. Some remarks: * Implicit in what I read, but it seems that master/slave choices are a property of the circuit design, i.e. they won't change during operation. As a consequence, all signals are uni-directional. It also seems plausible that a "dumb" device like a sensor or storage device will not be master. * When a slave is not enabled (SS high) the MISO (a.k.a. SDO) pin is in high-Z configuration. Does this require a pullup/down on the bus to avoid noise? I guess not as the input can be ignored by the master during the time no slave is active. * Communication is full duplex when the master drives the clock. There are 4 clock modes: 2 clock polarities times 2 read/write edge configurations. * Data seems to be MSB first (from SST25 and PIC18 data sheet). However SPI transfers bits, not bytes or words so it seems to be up to the device. * PIC18F2620 can use TMR2 / 2 or FOSC / 4,16,64 as master clock freq. ( While the other times have 2^n subdivisions, TMR2 has a period register so can be quite flexible. ) * In both the PIC18 and AT91SAM7 data sheets the master mode sends 8 bits at a time, sending MSB first. ( The PIC18 has one dead cycle after the 8th bit is sent out with the last asserted data bit still present. I've seen this using the SPI out as a video shift register. Since this is also a dead clock cycle, it doesn't matter for slaves. ) [1] http://en.wikipedia.org/wiki/SPI_bus Entry: Synth bus Date: Sat Feb 5 12:51:23 EST 2011 Insead of I2C it seems better to use a daisy-chained SPI bus, as it is easier to transport fixed sample rate PCM signals using circuit-switching. Entry: New PIC18 chip : PIC18F14K22 Date: Sat Feb 5 16:39:02 EST 2011 PIC18LF14K22-I/P * 20 pins, PDIP available * nanowatt XLP * internal oscillator up to 64MHz (16MIPS) * 64MHz (16MIPS) at 3V * 1.8 - 5.5V * SPI/I2C http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en538160 PIC18LF46K22-I/P, as above except: * 40 pins, PDIP available * 2x SPI/I2C 2xUART * 28 ADC channels http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en547757 That one caught my eye, but there are many more. Might need to do a sheepsint update ;) EDIT: looks like these new chips are not supported by PK2. They are still supported in the ICD2 though. But then the PK2 product page says it can debug the PIC18F46K20. Entry: Prototyping fear Date: Sat Feb 5 22:08:19 EST 2011 Next thing to do is to get over my prototyping fear. Basic problem is that I'm still very error prone and not so systematic building prototypes. I loose a lot of time fretting over things because change is expensive too. This is a problem and needs to be solved. Entry: Bitbang SPI on FT232RL Date: Fri Feb 11 07:00:34 EST 2011 Since I have several of these FTDI USB TTL cables it might be interesting to standardize on a connector for SPI. Is there anything that already does this? See [1][2]. So for SPI, the mapping that makes most sense is: TXD MOSI RXD MISO RTS SCK CTS CS with possibly SCK and CS swapped. [1] http://www.ftdichip.com/Support/Documents/AppNotes.htm [2] http://hackaday.com/2009/09/22/introduction-to-ftdi-bitbang-mode/ Entry: Fix electronics prototyping Date: Sun Feb 13 20:54:06 EST 2011 I was watching [1]. It was a bit disappointing after all the big words in the abstract. And as he explained in the talk: it doesn't solve vias. However, his problem exposition in the beginning is spot on though: electronics prototyping sucks. What is needed is something thoroughly different. I don't think it's possible to improve on PCBs for mass production, but for prototyping they suck. Fixing the prototyping problem would mean a revolution. What struck me in the talk is that you really just need to solve the 3D printing problem, where your "bricks" are 2 kinds: conducting and non-conducting. In this case you don't even need layers, just a possibility to cross wires, i.e.: . . . . . . X X X . . . . . X o X . . . . . here "X" is the insulator, and "." and "o" are the conducting wires. So instead of printing with voxels (volume pixels), why not print with wire strips? If there is no etching, there is no need for rounded corners, and a grid can be used. * Pick-and-place machine that places small pieces of wire on some kind of (embossed?) substrate, and then point-solders them where they need to be joined. * Cutting trenches, filling with molten metal? * Start with a patterned pcb and cut traces? [1] http://events.ccc.de/congress/2010/Fahrplan/events/4099.en.html Entry: Building GDB for arm-eabi Date: Tue Feb 15 15:47:07 EST 2011 # It's actually quite straightforward: wget http://ftp.gnu.org/gnu/gdb/gdb-7.2.tar.bz2 tar xf gdb-7.2.tar.bz2 mkdir -p gdb-7.2/build/arm-eabi cd gdb-7.2/build/arm-eabi ../../configure --target=arm-eabi make sudo cp gdb/gdb /usr/local/bin/arm-eabi-gdb-7.2 EDIT: make sure XML support is enabled (will do by default if libexpat-dev is installed) otherwise the openocd -> gdb memory map transfer won't work which breaks many things. EDIT: to enable python extension (apt-get install python-dev) ../../configure --target=arm-eabi --with-python Entry: Microchip idVendor sublicense Date: Thu Feb 17 11:08:53 EST 2011 It's possible to ask Microchip for a free product ID under their vendor ID 0x04D8 for product quantities under 10000. They reserve the right to revoke at any time. [1] http://ww1.microchip.com/downloads/en/AppNotes/Application%20for%20USB%20Vendor%20ID%20Sublicense.pdf Entry: Soldering SOIC Date: Sat Feb 26 23:04:19 EST 2011 Valt reuze mee! It's not such a big deal. Up to now my shaky hands have only attempted DIP soldering. However, for a contract job I was not able to find DIP components for prototyping, so I had to get over my SMD fear. 1. Dead-bug + AWG30 kynar wire wriap wire. Because I had no boards at all, this is what I tried first. The soldering by itself wasn't so hard: just make sure there is a bit of solder on the iron and touch the wire and pin. Getting the wire and pin to sit still is another matter. A 2-arm helping hand is what works well here. 2. SOIC -> DIP adapter. I followed the advice from many tutorials online: put a good amount of flux on the pads (I use a nail polish bottle & brush) and place the component on the pads. The flux will make it stick a bit, but you can still move it around. Solder one pin on one corner. I had to press the chip down to make sure it didn't slide, as my shaky fingers would push it out of place when I hit the side. If it doesn't move any more, solder the opposite corner. Be very careful not to bump the chip causing misalignment. Once two corners are fixed, just add some flux on the pins, put some solder on the tip (I'm using a slanted flat tip) and heat the pins one by one, boiling the flux. I don't think I'll be using the dead-bug style again. While straightforward, it is a lot of work stripping & aligning wires, and the result is fragile. Small adaptor boards are cheap on ebay. Entry: ARM in SOIC Date: Sat Feb 26 23:21:19 EST 2011 Luminary micro[1]. [1] http://www.luminarymicro.com/products/lm3s101.html Entry: SPI SRAM Date: Sun Feb 27 14:29:02 EST 2011 The Microchip 23A256 256kbit SPI SRAM[1] arrived. I wonder if I can use this to implement a TV/VGA frame buffer. Does it support continuous bit stream to dump out serial bits without any gaps? If so, readout can be used to draw scan lines, and the dead time can be used to upload data. In the datasheet[2] it is mentions that it supports sequential operation, so giving it a proper clock will just dump out all the bits. The remaining problem is then to detach the RAM SPI data output from the frame buffer output when we're updating. This can be done using a simple resistor connected to a PIC pin that's kept floating when the RAM is supposed to drive the output, and tied high or low when it is not. Other applications are 1 bit sample playback. [1] http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en539040 [2] http://ww1.microchip.com/downloads/en/DeviceDoc/22100E.pdf Entry: Binary modulation Date: Sun Feb 27 14:43:45 EST 2011 What about this: use a pre-computed modulation pattern stored in a SPI Flash, off-line optimized for a certain circuit. Even on-board flash and the synchronous output port could work fine.. Entry: Analog audio in Date: Sun Feb 27 19:14:08 EST 2011 The trouble with DIY measurement gear is always the front end, and getting the data in the computer. For the PIC18 my current option is only 12Mbit USB (full-speed). Ethernet is possible, but only at 10Mbit. So the PIC doesn't seem to be a good solution for anything more than audio rate. I've rencently been using AT91 for a project. I have a AT91SAM7X-EK board with 100Mbit ethernet. The USB only goes up to 12Mbit also. So two questions: * What is the fastest rate the AT91 can send? * What is the max sample frequency of the ADC? 1.25 uS conversion time 384 ksps The ADC speed isn't so high. Max data rate (10 bits) is just below 4Mbit. There should be no reason that doesn't work.. Entry: Upgrading OLS firmware Date: Sun Feb 27 23:20:40 EST 2011 $ svn checkout --username anonymous http://gadgetforge.gadgetfactory.net/svn/butterflylogic//trunk/package/OLS_Upgrader $ cat vars.sh export PATH=`pwd`/linbin64:$PATH $ sh ols-upgrader.sh I'm not sure if it worked correctly, but at least I don't get garbage any more when enabling RLE. The upgrade gave the following message, but I guess that's the old FW. ... Logic Sniffer ROM loader v0.3 (November 9, 2010) Opening serial port '/dev/ttyACM0' @ 921600 ... OK Found OLS HW: 1, FW: 2.3, Boot: 2 Found flash: WINBOND W25X40 OLS switched to bootloader mode ... Entry: OLS clocked input Date: Tue Mar 1 23:30:05 EST 2011 It would be very useful to be able to gather data with one of the pins acting as a clock input. [1] http://www.delicious.com/doelie/openbench Entry: DC amp Date: Thu Mar 10 20:27:10 EST 2011 For 9V battery-powered circuits it might be simplest to use a buffered 100k/100k voltage divider as the GND connection for inputs and outputs. It might introduce offset for high gain apps, but it does away with capacitors and biasing issues. Trouble is that you can't use the TRS jack trick to power on the circuit. Entry: Phantom power Date: Tue Mar 15 20:29:01 EDT 2011 I need a DI box and I'd like to feed it from the mixer's phantom power as I don't want to mess around with batteries that go dead or power supplies that can introduce more ground loops. Something like this[1]. Hmm.. Shopping around I find a cheap transformer-based passive one[3]. EDIT: actually, it's only a couple of milliamps. Closed circuit 14mA if the spec is followed. [1] http://www.amazon.com/Rolls-ADB2-Phantom-Direct-Box/dp/B00102VVZA [2] http://en.wikipedia.org/wiki/Phantom_power [3] http://pro-audio.musiciansfriend.com/product/Live-Wire-Solutions-SPDI-Passive-Direct-Box-with-Attenuation-Pad?sku=150449 Entry: Mixer feedback Date: Thu Mar 17 09:45:40 EDT 2011 I had some fun yesterday with the new Behringer Xenyx 802 mixer, some patch cords and a distortion pedal. The mixer has only one effects send which I used to feed the distortion pedal. See description[1] and recording[2]. This makes me think that an interesting application would be to build a circuit that has this kind of patching hard-coded, and just play with the feedback gains. To some extent it might be possible to automate the "chaos search". What I do manually is to turn some knobs and look for transition points. Then I apply minuscule changes to find the chaotic regions inbetween. [1] http://mala.wha.la/pool/moderately-extraterrestrial.txt [2] http://mala.wha.la/pool/moderately-extraterrestrial.ogg Entry: Unofficial PIC18 BDM debug module desciption Date: Sun Mar 20 22:54:22 EDT 2011 Jaromir Sukuba has published some info on the PIC18 in-circuit debugger functionality[1]. Great! [1] http://jaromir.xf.cz/hdeb/bdm/bdm.html Here's a mirror: ----------------------------------------------------------------- This page contains material which is derived partly from public domain information, but mostly guessed only. It seems to work, however. Use this information at your own risk, for personal research and personal use only. Author is not responsible for any damage, like broken PICs, crashed computers, sleepless nights, unsatisfied wives etc... No commercial use allowed. Microchip encorporates background debug module (BDM) module in all PIC18F devices, enabling them to be debugged in circuit. First device having BDM on board was PIC16F877 and derivatives - and this is the last device with offcial BDM module description. Following devices kept this secret, also all members of newer PIC families were released without description how their debug module works. I'll try to do this for PIC18 devcies in this document. Entering debug mode ------------------- For using debug mode, two conditions had to be satisfied: * disabling all code protect bits in configuration bytes * programming DEBUG configuration bit into logical 0 (this forces RB6 and RB7 to debug IO pins) There is reset (POR, MLCR or by executing RESET instruction) after programming, before entering debug mode. Actual entering debug mode is done in one of four ways: 1. by introducing 1->0 transition on RB6 pin 2. on POR/MCLR reset 3. on breakpoint 4. or after executing any instruction while single stepping is active First two conditions can be achieved without prior entering debug mode, another two (setting breakpoint or enabling single stepping) are possible only during debug mode. Entering BDM means entering vector at address 0x200028. There must be instruction to jump at address in valid FLASH range, where debug executive resides. Leaving debug mode ------------------ Once debug mode entered, it can be left by executing undocumented TRET instruction. This instruction seems to be identical to RETURN instruction, but it also clears DEBUG, INBUG bit. Opcode for TRET is 0x00E1. BDM registers ------------- BDM is controlled by one main register and three shadow registers. Main control register of BDM is DEBUG register at address 0xFD4 (notice gap at SFR map in all PIC18F devices). DEBUG (0xFD4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 INBUG FRZ SSTP SHDW BRB7 BRB6 BTS7 BTS6 INBUG - this readable bit is set in debug mode and clear during executing user code FRZ - this bit is clear by default. Setting this bit enables peripheral freezing in debug mode SSTP - this bit is clear by default. Setting this bit enables single step operation. After return from debug mode, only one instruction will be executed before entering debug mode again. SHDW - this bit is clear by default. Setting this bit enables shadow registers BDMSR0, BDMSR1, BDMSR2 BRB7 - bit to manipulate RB7 in debug mode, without affecting actual content of POR TB,7 register BRB6 - bit to manipulate RB6 in debug mode, without affecting actual content of PORTB,6 register BTS7 - bit to manipulate TRISB7 in debug mode, without affecting actual content of TRISB,7 register BTS6 - bit to manipulate TRISB6 in debug mode, without affecting actual content of TRISB,6 register There are also at least three shadow registers, accessible only when DEBUG,SHDW bit is set: BDMSR2 (0xFB9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? BKA19 BKA18 BKA17 BKA16 BDMSR1 (0xFB8) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKA15 BKA14 BKA13 BKA12 BKA11 BKA10 BKA9 BKA8 BDMSR0 (0xFB7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BKA7 BKA6 BKA5 BKA4 BKA3 BKA2 BKA1 BKA0 BKA[19..0] forms 20 bit wide register, holding address of breakpoint. When PC=BKA, BDM takes control and debug mode is entered. ? fields are bits with unknown meaning, for now. Don't touch it. Communication with target device -------------------------------- All communication with target device is done by RB6 and RB7 lines and MCLR. Before entering debug mode, target device (TD) has to be programmed using ICSP, so debugger implemntation has to contain also programmer implementation. Except of user code, TD has to have two additional regions programmed - debug vector and debug executive, for PIC18Fxxxx devices. For PIC18FxxJxx devcies, there are differences, covered later. Debug executive (DE) is program, which takes control after entering debug mode by BDM in TD. Its function is to communicate with debugger by RB6 and RB7 lines, using custom protocol. BDM does not support this communication by any way other than providing bits to manipulate with those pins and appropriate TRIS bits (see description of DEBUG register). Best place for DE is last few pages of FLASH memory, in order to not interfere with user program. Properly written DE can be smaller than 512B, or 256 program words. Debug vector (DV) is single instruction to redirect program execution into DE after entering debug mode. Memory region where DV resides, is ordinary FLASH block and must be erased and written in the same way as any other FLASH block. For PIC18FxxJxx devices, region where DV resides, is larger and complete DE will fit here (If you look at MPLAB help, you can find table about which resourced are consumed in order to use ICD. Those ones with no FLASH consumed allow to put complete DE into DV region). After programming (using ICSP) user code, DE and DV, MCLR has to be toggled to start execution of code. After reset, BDM takes control, forces PC to DV, where it executes instruction to enter DE in FLASH memory. Here is the point, where DE takes control and is fully responsible for communication with debugger. The same process is executed after introducing falling edge at RB6 pin, while running user code (this can be used to stop program flow). In all cases, except of POR or MCLR RESET, before forcing PC to DV, current PC value s saved on stack and stack pointer is incremented, so that TRET instruction can revert PC value to point before execution interrupt. After POR or MCLR reset, stack pointer is equal to zero, so TRET instruction can't do this. Because of this, DE has to check stack pointer and when it is equal to zero (situation after MCLR or POR reset), it has to increase stack pointer and clear TOSL, TOSH and TOSU registers - this forces PC return to correct address 0 after leaving DE. It is good idea to use both RB6 and RB7 pins to create simple bidirectional synchronous (in order to be not dependant on target clock) serial protocol. From protocol point of view, DE could be quite simple. Reading and writing registers, FLASH and EEPROM should be implemented, along with setting breakpoint address or single stepping. On debugger side, it is a bit more complicated. What is missing here -------------------- As a lot of those information are guessed only, it is incomplete. For example, I don't know how to set more than one breakpoint - for devices which allow more than one breakpoint. If you have further information to improve this document, contact me. How to... I made small handheld debugger which allows editing source code, assembling it, flashing into program memory and debugging of PIC18xxxx, PIC18FxxJxx and PIC18FxxKxx devices. It employs all priciples described above, you can find also source codes for both DE and debugger part. Updated 18.3.2011 Entry: I2C arbitration Date: Mon Mar 21 09:04:41 EDT 2011 How does send/receive arbitration work on I2C? According to [1], usually devices take on a single master or slave role, but they can switch between read and write. Looking at the PICkit spec PICkit2SourceGuidePCv2-52FWv2-32.pdf from [2] it seems that I2C uses the ICD AUX(6) pin which is normally LVP. [1] http://en.wikipedia.org/wiki/I2c [2] entry://../staapl/20080818-165846 Entry: Next hardware projects Date: Mon Mar 21 09:38:00 EDT 2011 1. Synth controller / calibration. This is a circuit implementing a collection of haptic-band (< 200Hz) DACs using class-D drivers connected to exponential sawtooth VCOs, using square wave frequency feedback for calibration. Requirements: - Staapl multi-PIC monitor, i.e. I2C - USB for monitor + MIDI 2. Staapler. This is a circuit implementing an alternative programmer that works better with Staapl. This could use PK2 firmware but probably needs dedicated firmware to be effective. Will support only limited set of chips since it's probably best to incorporate virgin chip programming. To get this going, make a test board with 2 PICS, one to act as a programmer, and one as a slave. A simple circuit is possible if I use LVP on the slave PIC. A PK2 with modified firmware is probably best, but is more work to get going. A PK2 with v2 firmware should be enough. Here, using the standard 20bit protocol is probably best, as it's best supported. Last time I got stuck on getting the bit-banged async serial to work reliably. Components: - USB driver - I2C monitor It looks like the USB driver is going to have the highest payoff, as it would avoid the necessity of building new boards. It also seems like the most work. Reusing a PK2 v2 and sticking to something that can use the programming protocol seems to be the best approach. So let's revive the pk2 code first. Entry: Rigol DS1052E Date: Fri Mar 25 22:44:18 EDT 2011 The scope arrived. I payed about $400. Dollar/Euro is at 1.4 today so this is really quite a deal. Played with it a bit, and it seems to be quite nice. First thing I did (after FFTs on 60Hz mains) is to hook it up to the serial port of my PIC18F2550 setup to test the trigger mode. I noticed some 100ns rise time spikes of about 1.3V. What's that about? They consistently happen at regular intervals after the normal serial transitions (baud at 230k4). Cable reflections? Looks like it. Distance of the spikes is 188us. Entry: Rigol remote control using usbtmc Date: Sat Mar 26 16:07:07 EDT 2011 Quite straightforward. It's almost like a serial terminal, but usbtmc seems to be message based, and there is timing information. However using the character device, all of the complexities of the usbtmc protocol are hidden. I'm using this[1] quick-hack to query the device: tmc # send command tmc -r # .. and print reply Useful commands *IDN? Identitiy *RST Reset :RUN Start capturing / wait for trigger :STOP Stop capturing :AUTO Autoset :TRIG:EDGE:SWE SING Single shot :TRIG:EDGE:SWE AUTO Continuous display To get waveform data: :WAV:POIN:MODE NOR :WAV:DATA? CHAN1 That first command I got from here[2]. I didn't find it in the manual. The second one only makes the 2.05 SP2 crash. I wonder how to download the entire data buffer.. Manual doesn't seem to be complete. Btw, it's great to have [1] sending ":RUN" to the scope to arm the trigger, with that command bound to a key in emacs. [1] http://zwizwa.be/darcs/pool/src/tmc.c [2] http://www.cibomahto.com/2010/04/controlling-a-rigol-oscilloscope-using-linux-and-python/ Entry: Jeri's toy stories Date: Mon Mar 28 15:10:16 EDT 2011 In the toy industry, it's not time-to-market but cost that's most important according to Jeri Ellsworth[1]. [1] http://www.theamphour.com/2011/03/21/the-amp-hour-35-the-ternary-tussle/ Entry: Electronics: There Is No Abstraction Date: Sun Apr 10 16:56:51 EDT 2011 Amanda Wozniak: Hardware Will Cut You[1]. A very true story about how electronics is not programming. The one that hit it on the head was: there is no abstraction. You have to think about everything all the time. [1] http://www.eevblog.com/2010/11/08/hardware-will-cut-you/ Entry: El-cheapo modular synth board layout Date: Sat Apr 23 00:48:38 EDT 2011 The missing link: a no-brainer connection strategy. When using a current in, voltage out approach, many circuits become simpler, and you get free fixed-gain configurability if you allow the resistors to be socketed. I.e. using a 3-hole configuration like: in Ra Rb o--o o--> vground A wire can be plugged into the input, and a gain resistor can be plugged across Ra/Rb. This layout has the advantage that it can accomodate both a proto-board and the final layout (simply hard-wire the connection and the scaling resistor). To make it even simpler the resistor can be omitted and be made part of the "patch cable", however that doesn't work well for simple fixed circuit boards. So a 3x1 100 mil through-hole array seems best. If all sockets are made female, patch wires can be made cheap (just stripped wire) and resistors go straight into the sockets. Entry: One circuit a day Date: Sat Apr 23 01:30:52 EDT 2011 I'd like to get out of cargo cult component fondling MO and into building working circuits. The following things I want: - Guitar headphone preamp. - El-cheapo modular synth. Both should run on the tiny perfboard I got, using standard TL072 opamps, of off 9V batteries. Entry: Opening up BeBook e-reader Date: Wed Apr 27 19:28:41 EDT 2011 - Take out the 4 cylindrical rubber plugs that cover 4 screws on the back. Remove 4 screws + one for the battery holder. - Use some sticky gum to temporarily attach the battery to the board otherwise it's dangling. - Take off the back cover by prying it open at the USB connector, then go around. - Serial console is at J8. Center is ground, closest to the label is TX the other end is (probably) RX. - The distance between the pads is not quite 100mil, more like 2mm. I used a 3-prong SIP socket and bent the wires a bit, then use jumper wires into a TTL serial female header plug. - The baud rate is 115200. - Plug in USB to prevent it from going to sleep. OK U-Boot 1.1.6-g1b97c629-dirty (Aug 24 2009 - 14:27:37) for SMDK2416 CPU: S3C2416@400MHz Fclk = 800MHz, Hclk = 133MHz, Pclk = 66MHz Board: SMDK2416 Mobile SDRAM DRAM: 32 MB NAND: 512 MB (Memory Based BBT Enabled) *** Warning - bad CRC or NAND, using default environment In: serial Out: serial Err: serial Battery Power : 4.01v 8 Gray Level Screen Supported! Hit any key to stop autoboot: 0 NAND read: device 0 offset 0x200000, size 0x1c0000 1835008 bytes read: OK Boot with zImage Starting kernel ... Uncompressing Linux....................................................................... done, booting the kernel. Linux version 2.6.21.5-cfs-v19 (maoyk@celling) (gcc version 4.0.0) #507 Wed Nov 4 13:30:36 CST 2009 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177 Machine: SMDK2416 Ignoring unrecognised tag 0x00000000 Memory policy: ECC disabled, Data cache writeback CPU S3C2416 (id 0x32450003) S3C24XX Clocks, (c) 2004 Simtec Electronics S3C2416: mpll on 800.000 MHz, cpu 400.000 MHz, mem 133.333 MHz, pclk 66.666 MHz S3C2416: epll on 192.000 MHz, usb-bus 48.000 MHz CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets Built 1 zonelists. Total pages: 8128 Kernel command line: noinitrd root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0 mem=32M irq: clearing subpending status 00000402 irq: clearing subpending status 00000002 PID hash table entries: 128 (order: 7, 512 bytes) timer tcon=00500000, tcnt 28af, tcfg 00000f00,00000000, usec 00007ae2 Console: colour dummy device 80x30 Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory: 32MB = 32MB total Memory: 30120KB available (1936K code, 291K data, 92K init) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 S3C2410 Power Management, (c) 2004 Simtec Electronics S3C2416: Initialising architecture S3C2416: IRQ Support S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics DMA channel 0 at c2800000, irq 88 DMA channel 1 at c2800100, irq 89 DMA channel 2 at c2800200, irq 90 DMA channel 3 at c2800300, irq 91 DMA channel 4 at c2800400, irq 92 DMA channel 5 at c2800500, irq 93 DMA channel 6 at c2800600, irq 99 DMA channel 7 at c2800700, irq 100 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered NetWinder Floating Point Emulator V0.97 (double precision) JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. io scheduler noop registered io scheduler anticipatory registered (default) io scheduler deadline registered io scheduler cfq registered S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics Founded postion :[11] Founded postion :[11] s3c2440-uart.0: s3c2410_serial0 at MMIO 0x50000000 (irq = 70) is a S3C2440 s3c2440-uart.1: s3c2410_serial1 at MMIO 0x50004000 (irq = 73) is a S3C2440 s3c2440-uart.2: s3c2410_serial2 at MMIO 0x50008000 (irq = 76) is a S3C2440 loop: loaded (max 8 devices) wake enabled for irq 50 wake enabled for irq 16 wake enabled for irq 17 wake enabled for irq 18 wake enabled for irq 19 wake enabled for irq 58 wake enabled for irq 59 wake enabled for irq 51 PPP generic driver version 2.4.2 PPP Deflate Compression module registered s3c2410 NOR-Flash Driver, (c) 2004 Simtec Electronics s3c2410-nor: Found 1 x16 devices at 0x0 in 16-bit bank Amd/Fujitsu Extended Query Table at 0x0040 number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. Creating 1 MTD partitions on "s3c2410-nor": 0x00000000-0x00200000 : "Boot loader" S3C NAND Driver, (c) 2007 Samsung Electronics S3C NAND Driver is using hardware ECC. NAND device: Manufacturer ID: 0xad, Chip ID: 0xdc (Hynix NAND 512MiB 3,3V 8-bit) Scanning device for bad blocks Creating 6 MTD partitions on "NAND 512MiB 3,3V 8-bit": 0x00200000-0x00400000 : "KERNEL" 0x00400000-0x00a00000 : "BASEFS" 0x00a00000-0x07d00000 : "ROOTFS" 0x07d00000-0x07e00000 : "LOGO" 0x07e00000-0x08000000 : "USERDATA" 0x08000000-0x1f000000 : "STORAGE" Loaded s3c-udc version Nov 4 2009 S3C24XX RTC, (c) 2004,2006 Simtec Electronics res->start : 57005000 res->end : 0<6>s3c2410-rtc s3c2410-rtc: rtc disabled, re-enabling s3c2410-rtc s3c2410-rtc: rtc core: registered s3c as rtc0 i2c /dev entries driver s3c2410-i2c s3c2410-i2c: slave address 0x10 s3c2410-i2c s3c2410-i2c: bus frequency set to 9 KHz s3c2410-i2c s3c2410-i2c: i2c-0: S3C I2C adapter wake enabled for irq 48 [s3c_hsmmc_probe]: s3c-hsmmc.0: at 0xc286c000 with irq 37. clk src: hsmmc Registered led device: nand-green-led-data Registered led device: nand-red-led-data Registered led device: mmc-green-led-data Registered led device: mmc-red-led-data Registered led device: charge-green-led-da Registered led device: charge-red-led-data Registered led device: lcd-green-led-data Registered led device: lcd-red-led-data Advanced Linux Sound Architecture Driver Version 1.0.14rc3 (Wed Mar 14 07:25:50 2007 UTC). smdk_audio_matchdev: dev=c020d948 ALSA device list: #0: S3C2410 TLV320 TCP cubic registered NET: Registered protocol family 1 NET: Registered protocol family 17 s3c2410-rtc s3c2410-rtc: hctosys: invalid date/time VFS: Mounted root (cramfs filesystem) readonly. Freeing init memory: 92K init started: BusyBox v1.8.2 (2008-12-03 22:38:29 CST) starting pid 238, tty '': '/etc/init.d/rcS' Make /etc writeable Remounting /etc as writeable ...... DONE vm.dirty_writeback_centisecs = 10 vm.dirty_expire_centisecs = 10 Mounting local filesystems... Starting system message bus: [ $OK ] starting pid 279, tty '': '/bin/autologin' Welcome to jinke ebook system... login[279]: root login on 'ttyS0' /bin/dbus-launch --exit-with-session Startx.... # Sending signal PowerChange with value PowerLevel4 nxclient: retry connect attempt 1 FAT: utf8 is not a recommended IO charset for FAT filesystems, filesystem will be case sensitive! open file:/root/appdata/fontlib.conf error wake enabled for irq 46 wake disabled for irq 46 wake enabled for irq 46 Stopping tasks ... done. Suspending console(s) s3c2410_pm_enter(3) s3c2410_sleep_save_phys=0x3167be5c Leaving IRQ 16 (pin 160) enabled Leaving IRQ 17 (pin 161) enabled Leaving IRQ 18 (pin 162) enabled Leaving IRQ 19 (pin 163) enabled Leaving IRQ 48 (pin 164) enabled Disabling IRQ 49 (pin 165) Leaving IRQ 50 (pin 166) enabled Leaving IRQ 51 (pin 167) enabled Disabling IRQ 57 (pin 197) Leaving IRQ 58 (pin 198) enabled Leaving IRQ 59 (pin 199) enabled sleep: irq wakeup masks: bffffff0,ffff3f2f [1] http://delicious.com/doelie/bebook [2] http://openinkpot.org/wiki/Device/V5/SerialPort Entry: Low power PIC tips Date: Thu May 19 23:07:08 CEST 2011 The PIC datasheets clearly state that non-digital signals (around 1/2 Vcc) should never be connected to a digital input to avoid linear biasing of the CMOS input state which draws a lot of power. However [1] mentions on page 2-4 that: "Sometimes it is appropriate and possible to configure digital inputs as analog inputs when the digital input must go to a low power state." Which vaguely implies that analog inputs consume less power than digital ones. If the inputs are logic-level (i.e. not 1/2 Vcc) then I doubt this is true. Maybe it's a safety measure in case the input starts floating? Or is it about the leak current of a CMOS input stage vs. that of an analog input stage? What do uC analog inputs look like? Are they comparator inputs? Those would be differential pairs. What about their bias current? Ha! It's not the ADC input that counts, but the analog MUX. I suppose the ADC input stage is simply off when not converting, not drawing any leakage current. For the PIC input pints, the only difference between analog and digital mode is that digital mode has power to the digital input buffer, so always uses more power (input buffer leakage). [1] http://ww1.microchip.com/downloads/en/DeviceDoc/01146B_chapter%202.pdf Entry: PIC ADC Date: Tue Jul 12 13:56:26 CEST 2011 When changing ADC channel (amux switch), it is necessary to wait a bit for the holding cap to charge. Entry: WDTV Live Date: Mon Sep 19 20:27:31 EDT 2011 Console connector: -- ----- -- | . . . . | | | --+-+-+-+-- 5 R T G V X X N D [1] http://www.legitreviews.com/article/1118/2/ Entry: Hooking up L78L33 3v3 regulator from 9V Date: Tue Sep 27 11:55:35 EDT 2011 See datasheet L78L33[1]. BOTTOM VIEW _________ \ 1 2 3 / \_____/ 1 = V_OUT 2 = GND 3 = V_IN These are from the test circuit. Not sure if necessary: C_IN = 0.33uF C_OUT = 0.100uF I' just put 2 1uF elcos on either side. Plugged it in wrong first (pic says bottom view!). It started smelling, got pretty hot. Still works after turning it around. [1] http://www.decelectronics.com/html/PDF/L78L33.pdf Entry: PICkit v2 wiring Date: Tue Sep 27 15:01:14 EDT 2011 >1 MCLR white 2 VDD red 3 GND black 4 PGD blue 5 PGC green 6 PGM ? [1] http://www.ianstedman.co.uk/Projects/TK3_PICKit2_adaptor/tk3_pickit2_adaptor.html Entry: Serial port hardware flow control Date: Wed Oct 19 12:38:02 EDT 2011 Something which has always confused me. See wikipedia[1]. For a null modem connection which seems to be my only use case, simply connect the RTS out of one side to the CTS in of the other and vice versa. /CTS input: other side ties low to indicate it can receive more data /RTS output: we tie low when we can receive more data. So what about DTS / DTR? It seems that these are connected to RTS and CTS for a non-symmetric (non-null modem) line. [1] http://en.wikipedia.org/wiki/RS-232_RTS/CTS#RTS.2FCTS_handshaking Entry: slow, synchronous bi-directional protocol Date: Sun Nov 6 13:15:45 EST 2011 I need something to connect 2 slow devices, meaning that neither end has a timing restriction and can take as long as it pleases inbetween protocol phases. This needs 4 lines on both ends, cross wired + ground. Let's do DR = data ready RA = read ack Dx = data out/in Timing diagram ___ ___ DR __| |___| |_____ DO /// /// ___ ___ RA ____| |___| |___ DI /// /// The problem with this is that it is not symmetric. It would be simpler to make it fully ping-pong and only trigger on edges: every transition on the sync line indicates that the next bit is valid. Here 'X' means a data transition, all the other states are valid. ___ ___ DR __| |___| |_____ DO 0 X 1 X 2 X 3 X 4 ___ ___ RA ____| |___| |___ DI 0 X 1 X 2 X 3 X 4 This is fully symmetric because only the edges count, not the levels. In receive mode, we wait for a clock edge, then read the data, write our data and flip our clock then switch back to receive mode. Once this is locked we have a bi-directional bit stream that can go arbitrarily slow. It probably needs some logical protocol on top of that for synchronization, to allow insertion of idle bit patterns. So how to start it up? Someone has to send the first edge, and it needs to know that the other side will see that edge, meaning it was listening. From there on it is straightforward, but that first start doesn't seem so simple. It needs extra starting conditions: - Who will send the first bit. This creates the initial a-symmetry to get the loop going: one will wait for reception and the other will cause the first write. - What edge will be used for the first bit. This is necessary to initialize the edge detector (differentiator). Entry: High-school electronics vocation Date: Thu Jan 12 11:51:09 EST 2012 Looks like I have the chance to participate in a High-school vocational electronics program. What to teach? The most useful seems to be Arduino, since it's gotten quite popular. I've never used it, so here it goes. I need to order an Arduino board, so want to know which one to order. There seem to be several varieties. Which one is best? - Latest: Uno[1] ATmega328[5] (main) + ATMEGA8U2[6] as USB serial converter. - Previous: Duemilanove[3]. ATmega168 or ATmega328 + FTDI. Others are here[4]. I don't see a point in getting any of the bigger ones, so it seems Uno is best. I got 2 on eBay here[2]. Also, some chips that are not code-compatible, but have the same header layout: - LeafLabs Maple r5 [1] http://arduino.cc/en/Main/arduinoBoardUno [2] http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=320828429181#ht_830wt_1112 [3] http://arduino.cc/en/Main/arduinoBoardDuemilanove [4] http://arduino.cc/en/Main/Boards [5] http://www.atmel.com/dyn/products/product_card.asp?part_id=4720 [6] http://www.atmel.com/dyn/products/product_card.asp?part_id=4600 Entry: LeafLabs Maple r5 Date: Thu Jan 12 12:52:19 EST 2012 ( TL;DR : Don't use the IDE. Follow instructions in [3]. ) I had some trouble with one particular usb port. Plugging it in a powered hub seems to solve the issue. Here's how it registers. [5020582.977878] usb 1-4.1.4.2: new full speed USB device using ehci_hcd and address 100 [5020583.087990] usb 1-4.1.4.2: New USB device found, idVendor=1eaf, idProduct=0003 [5020583.087993] usb 1-4.1.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [5020583.087995] usb 1-4.1.4.2: Product: Maple 003 [5020583.087997] usb 1-4.1.4.2: Manufacturer: LeafLabs [5020583.087998] usb 1-4.1.4.2: SerialNumber: LLM 003 [5020585.575876] usb 1-4.1.4.2: USB disconnect, address 100 [5020585.793800] usb 1-4.1.4.2: new full speed USB device using ehci_hcd and address 101 [5020585.906534] usb 1-4.1.4.2: New USB device found, idVendor=1eaf, idProduct=0004 [5020585.906537] usb 1-4.1.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [5020585.906539] usb 1-4.1.4.2: Product: Maple [5020585.906541] usb 1-4.1.4.2: Manufacturer: LeafLabs [5020586.229291] cdc_acm 1-4.1.4.2:1.0: ttyACM0: USB ACM device [5020586.230219] usbcore: registered new interface driver cdc_acm [5020586.230221] cdc_acm: v0.26:USB Abstract Control Model driver for USB modems and ISDN adapters I'd like to find out the following: - How to use the IDE[1] - How to bypass the IDE and build an eCos-based image and load it in DFU mode. First, switching to DFU mode is done by holding the button through a reset. Doesn't seem to work, neither with reset nor power cycle (unplug/replug USB). Doesn't seem to work on 64bit. tom@zoo:/opt/xc/maple$ ./maple-ide java.lang.UnsatisfiedLinkError: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so 32 (Possible cause: architecture word width mismatch) thrown while loading gnu.io.RXTXCommDriver Exception in thread "main" java.lang.UnsatisfiedLinkError: /opt/xc/maple-ide-v0.0.12/lib/librxtxSerial.so: /opt/xc/maple-ide-v : wrong ELF class: ELFCLASS32 (Possible cause: architecture word width mismatch) at java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.lang.ClassLoader.loadLibrary0(ClassLoader.java:1750) at java.lang.ClassLoader.loadLibrary(ClassLoader.java:1675) at java.lang.Runtime.loadLibrary0(Runtime.java:840) at java.lang.System.loadLibrary(System.java:1047) at gnu.io.CommPortIdentifier.(CommPortIdentifier.java:123) at processing.app.Editor.populateSerialMenu(Editor.java:795) at processing.app.Editor.buildToolsMenu(Editor.java:612) at processing.app.Editor.buildMenuBar(Editor.java:413) at processing.app.Editor.(Editor.java:187) at processing.app.Base.handleOpen(Base.java:608) at processing.app.Base.handleOpen(Base.java:573) at processing.app.Base.handleNew(Base.java:475) at processing.app.Base.(Base.java:245) at processing.app.Base.main(Base.java:149) So, running on 32bit with sun java 6 it comes up, but is hardly usable. The UI seems to be full of bugs... Though this could be Java interacting with XMonad, which I've seen do weird things before. Let's switch to emacs and command line tools. Seems that the only thing the IDE does is compile and upload. See reference/unix-toolchain.html [3] for info on using libmaple without the IDE. Tested: the first time I got a segfault in the dfu upload as part of "make install". After that it seemed to work. Looks like the rest should be straightforward: - Figure out the memory layout for the DFU image. - Figure out the upload protocol, i.e. how does it actually switch to DFU? - Does eCos have drivers for this chip? STM32F103RBT: Maple. STM32F103ZET6: eCos port for the STM3210E-EVAL[4] board. These seem to be similar enough to at least give it a try. Essential devices seem to be supported: tom@zoo:~/ecos-build/src/cvs/packages/devs$ find -name '*stm32*' |grep cdl ./flash/cortexm/stm32/current/cdl/flash_stm32.cdl ./usb/cortexm/stm32/current/cdl/usb_stm32.cdl ./spi/cortexm/stm32/current/cdl/spi_stm32.cdl ./adc/cortexm/stm32/current/cdl/adc_stm32.cdl ./serial/cortexm/stm32/current/cdl/ser_cortexm_stm32.cdl ./wallclock/cortexm/stm32/current/cdl/wallclock_stm32.cdl Next: - build eCos config - port LwIP to maple? [1] http://leaflabs.com/docs/maple-ide-install.html#maple-ide-install-linux [2] http://wiki.openmoko.org/wiki/Dfu-util [3] http://leaflabs.com/docs/unix-toolchain.html [4] http://www.st.com/internet/evalboard/product/204176.jsp Entry: Linux host for USB debugging Date: Thu May 17 13:20:47 EDT 2012 I'm writing firmware for a USB device. It would be useful to now be able to run a kernel inside a debugger to see what's going on, and maybe to freeze the enumeration process. I don't want to do this on my development host because I might crash the kernel. I was thinking user mode linux or KVM for debugging, but it doesn't look like that's going to work. It seems to me that all emulation will just pass USB stuff to the hosts' usb layer, and that's exactly what I'm trying to debug. Maybe its best to do this on a real host with some kind of kernel debugger or at least a bunch of logging? This needs: - A real host with usb subsystem as modules - Probably compiler on the real host I have an old dell laptop to set this up. Let's give it a try. First, lets backup. apt-get source linux-2.6 Once configured, to build only a single subdirectory, use. make modules SUBDIRS=drivers/the_module_directory I don't know how to configure a linux tree though.. maybe just building it with kpkg-deb ? I'm just using "make menuconfig" default now. make oldconfig make prepare make modules SUBDIRS=drivers/usb/host I have both uhci_hcd and ehci_hcd. Which is it? Stuff seems to work without ehci_hcd. It seems to work with only uhci_hcd, USB 1.1 drivers/usb/host/uhci-hcd.c The error messages like: [ 8007.022046] usb 1-1.4: device descriptor read/64, error -71 come from drivers/usb/core/hub.c Maybe it helps plugging it in directly to the 64bit host? Entry: USB debugging Date: Fri May 18 14:01:38 EDT 2012 broebel:~# mount -t debugfs none_debugs /sys/kernel/debug broebel:~# sudo modprobe usbmon broebel:~# cat /sys/kernel/debug/usb/usbmon/1u | tee /tmp/usbmon_1u.log Entry: USB protocol info Date: Sat May 19 14:54:26 EDT 2012 A 0 is introduced after 6 consecutive one bits to ensure enough transitions. To decode this, just do the reverse: if 6 consecutive one bits are received, drop the following zero. If 7 consecutive ones are detected a bit stuffing error is raised an the packet is discarded. A packet on the wire is a NRZI encoding of a packet, prefixed with a clock sync pattern. See 7.1.9 in USB1.1 spec [1]. From 8.4.5.4 in [1] it says that SETUP is a special kind of OUT that resets the data sync. SETUP token is always followed by a DATA token. From 8.5.2 in [1]: Control Transfers Control transfers minimally have two transaction stages: Setup and Status. Setup is SETUP + DATA0. The Status stage is delineated by a change in direction of data flow from the previous stage and always uses a DATA1 PID. The terms are a bit confusing: transaction, sequence, token, .... Anyhow, it seems that I don't need to care about ACK. So, a "stage" is actually two tokens: SETUP, DATA0 OUT, DATAx IN, DATAx The SETUP, OUT, IN tokens are always sent by the host. The DATAx tokens are sent by the host if preceded by SETUP and OUT, or by the device is preceeded by IN. ( On the PIC, these stages are atomic. ) Questions: - In figure 8-12 [1], does a DEVICE GET_DESCRIPTOR request have a data stage? I.e. is it a Control Read or a No-Data control - Is the Status IN always empty, or can it have a payload? [1] http://esd.cs.ucr.edu/webres/usb11.pdf