( -*- forth -*- ) load stc/stc.f ( midi filter. host midi i/o: uart/usb 8 filtered out: bitbanged + several other inputs/outputs main program: transpose input to filtered start - data - stop bits for output port. timer interrupt at 31250 hz: [ 1/32 MHz ] outputs one splatted bit at a time fast interrupt: W <- state PCL += W * high speed uart input interrupt -> in buffer * main loop: interpret forth + midi + write to 8 output regs * bitbang 8 out interrupt. for each byte, synchronous state machine: startbit, 8xdata, stopbit. all using mask. PLAN - start with non-buffered forth monitor, write output routine - add buffering to input monitor - replace monitor with unidirectional midi input ) ( bit transpose? shift to/from carry can be done in isr or in in mainloop code: transpose + init transmit state machine + set data ready maybe best in isr: not much buffering necessary ) host ( compile bit shifter ) : shifter# ( address bits -- ) accept (tword) dup, 0 movlw, clc, for dup rrcf, f, WREG rlcf, 1 + next drop ;, ; target ( bits -- ) : shift> >x 0 clc xfor [ POSTINC2 rrcf, f, WREG rlcf, ] next ; 0x10 8 shifter x application : main [ 0x10 ]a! 8 shift> main ; savehex midi.hex