Building a Digitally Controlled Analog Synthesizer In '95, when I was 20 years old and had completed the first 2 general years of engineering study, I decided to specialize in electronics for two reasons: I thought I was a good enough programmer to not need a degree in computer science (the arrogance!), and I wanted to learn more about electronics to design and build an analog synthesizer. Studying electronics, I gravitated towards digital signal processing, away from the analog electronics that lured me in. The pain induced by writing signal processing code in C/C++ turned into a motivation to spend a some years on study of programming language theory and compilers, far away from electronics. So now, going into 2011, a little over 15 years after the initial decision to get into analog electronics I am getting into analog electronics! This blog is a spin-off of a more general electronics[1] blog, and comes with a collection of circuits to be found here[2]. [1] entry://../electronics [2] http://zwizwa.be/darcs/analog Entry: The 909 kick drum Date: Sun May 2 17:06:25 EDT 2010 Some schematics[1][2]. These seem quite involved. [1] http://www.analog-synth.de/synths/tr909/tr909.htm [2] http://www.introspectiv.eclipse.co.uk/ Entry: Broken PAIA Fatman Date: Sat May 15 17:52:49 EDT 2010 I have two Fatman kits, one built but broken (probably uC died trough short-circuit) and one not assembled. Plan: order a desktop case for the packaged kit + try to get the built one working with a PIC controller. DAC = floating point: note select uC P36 and P34-P35 for octave select. Trying 13.5 MHz xtal with 4550. This won't work with fixed frequency 96 MHZ PLL, which needs a 4MHz input. FIXED: using 8MHz XTAL. 4550 OK @ 230400 baud. Next: Fatman power supply. Done. 12V AC connected, and the oscillators seem to work. Next: envelopes. Both A(S)R for VCF and ADSR for VCA are on when inputs = 0V, which is the reason it sounds when the pins are not driven; they go to NPN base. PIC pinouts reserved: - serial comm - PWM - analog in - 1 interrupt for serial envelope: - 3 OUT - 2 IN (envelope interrupt) CV: - 12 OUT: 8 (NOTE) + 2 (OCTAVE) + 2 (S/H) - 74HC373 can be patched through (use SH for setting CVs) PIN allot - RB7,6,5 as inputs for 2x envelope in and 1x midi in. MIDI @ 38400 baud / 12MIPS is DIV=312.5 - RA0,1,6 as outputs for envelopes. next: A(S)R input : O15 (P31) -> RA4 (P6) works, after fixing the +8 volt connection Entry: FM on PIC Date: Tue May 18 23:39:34 CEST 2010 Instead of focussing on one thing, digging up the fatman makes me think of building more synths. Can standard FM be run on a PIC chip? I guess so, as long as we stick to 8 bit sample resolution, and can stick to 8x8 multiply. At 12 mips there's quite some headroom. Entry: VCF using modern parts Date: Wed May 19 01:50:46 CEST 2010 I'm thinking about how to build synths with modern components. Main problems are the VCF and envelopes. Oscillators might be best done digitally. I found some SSM2164 quad VCA under the dust which I think was planned to be used as such before I forgot about them. How to use these as VCF? Maybe the datasheet has some circuit? No. This has [3]. Maybe a single SSM2164 can be used for a 3-pole SVF and a VCA? The SSM2164 can run on a single supply down to 8V using a VCC/2 opamp buffered reference voltage. [1] http://matrixsynth.blogspot.com/2009/03/ssm2164-thvcf-clone-with-modulation.html [2] http://www5b.biglobe.ne.jp/~houshu/synth/ [3] http://userdisk.webry.biglobe.ne.jp/000/024/65/1/VcfSSM0602a.GIF Entry: Analog Box Date: Fri May 28 14:41:24 CEST 2010 These are in the analog box: MAX336 16 chan analog mux MAX274 4x 2nd order analog filter SSM2164 4x VCA AD633 analog multiplier MAX265 2x 2nd order switched cap DS1666 log digital resistor MAX174 1chan 12bit ADC MCP4922 12 bit DAC SPI and a bunch of 555-style timers. Entry: Programmable gain amplifiers Date: Tue Oct 19 01:34:43 CEST 2010 To make some noise with digitally controlled analog circuits, it might be interesting to look at programmable gain amps that can be inserted into SVF filter feedback loops. Maxim has some. What this needs is dynamic range. The MAX9939[1] might be an intersting candidate, however it has only 10 settings. Can such a thing be modulated? Another one is DS4420[2] which has a 60dB/3dB scale. Maybe a digi pot is better[3].. This goes to 1024 steps linear and 128 steps log. I've ordered samples for DS1807[4] and DS1801[5]. [1] http://www.maxim-ic.com/datasheet/index.mvp/id/5825 [2] http://www.maxim-ic.com/datasheet/index.mvp/id/5218 [3] http://para.maxim-ic.com/en/results.mvp?fam=dig_pot [4] http://www.maxim-ic.com/datasheet/index.mvp/id/2782 [5] http://www.maxim-ic.com/datasheet/index.mvp/id/2777 Entry: Modifying Behringer pedals Date: Sun Nov 21 22:15:38 EST 2010 Instead of buying cases to fill with custom electronics, it seems simpler to just buy a cheap Behringer pedal and replace the innards. They are $24 at americanmusical.com Cases seem to be plastic though.. The OD300[2] is a simple distortion an has 4 equal size knobs. Seems like the best choice. Some inside pictures of a DC9[3] and a PH9[4]. They seem to be for real; not all digital. [1] http://www.americanmusical.com/ItemSearch.aspx?search=behringer+pedal&srcin=1 [2] http://www.behringer.com/DE/downloads/pdf/OD300_P0608_M_EN.pdf [3] http://www.tdpri.com/forum/stomp-box/244312-behringer-photos-inside-cheap-pedal-fun-spray-paint.html [4] http://www.diystompboxes.com/smfforum/index.php?topic=67769.0;prev_next=prev Entry: PT2399 digital delay IC (Danelectro FAB Echo) Date: Tue Nov 23 12:59:48 EST 2010 Ordered the FAB Echo for $15 [3]. At first sight this seems to be a digital delay line with an R-tunable oscillator for the digital machinery. I wonder why the digital oscillator frequency is so high though: 2-20MHz as mentioned in [1]. Is this a sigma-delta delay line with the signal stored in binary? [1] http://www.futurlec.com [2] http://www.diystompboxes.com/smfforum/index.php?topic=64519.0 [3] http://guitars.musiciansfriend.com/product/Danelectro-FAB-Echo-Guitar-Effects-Pedal?sku=151844 [4] http://www.uni-bonn.de/~uzs159/pt2399.html Entry: uC controlled analog circuits Date: Tue Nov 23 12:51:48 EST 2010 The goal is to build something that can control an analog circuit through a PIC uC. The path I'd like to take is some SVF filter with variable feedback, using a digital resistor as the control signal D/A converter. Rationale: It doesn't seem to be so simple to get OTA ICs these days to build VCA, VCF circuits which have variable gain, so let's list some options: - transconductance-based VCA (transistor or OTA) - VCA circuits - digital resistors The problem is resolution. If the control envelopes are also generated using analog circuitry that's not such a problem, but it then does require a proper VCA. Ok, let's try the digi pot. I have DS1807[1] and DS1801[2]. Looks like the DS1801 is more appropriate as I don't need the addressing. It has a cool feature: zero crossing detection with a 50ms delay. Questions: - Which PIC to use (18F1320) - How fast does the 1801 switch? - Use a filter IC or opamps? - Max voltages on resistor terminals? Switch frequency: the serial clock can go up to 10MHz (bit = 100ns), there are 16 bits to transfer and the latch time is 200ns, so max rate is 555kHz. That should be enough to do any kind of interpolation PWM/SD modulation. The question with modulation is: how do glitches behave? For use as input current feedback resistors Using the PIC's HW shift register limits the debug interface. [1] http://www.maxim-ic.com/datasheet/index.mvp/id/2782 [2] http://www.maxim-ic.com/datasheet/index.mvp/id/2777 Entry: Modular channel strips Date: Wed Nov 24 22:11:00 EST 2010 Some modular way to build mixers. It's interesting to see how a big mixer can be intimidating, but a tiny one that can be "added to" is not really.. Entry: That VCA Date: Sat Nov 27 16:43:22 EST 2010 2180[1][4], 2181[2], 2162[3]. [1] http://www.thatcorp.com/2180-series_Pre-Trimmed_Blackmer_IC_Voltage-Controlled_Amplifiers.shtml [2] http://www.thatcorp.com/2181-series_Trimmable_Blackmer_IC_Voltage-Controlled_Amplifiers.shtml [3] http://www.thatcorp.com/2162_Dual_Pre-Trimmed_Blackmer_IC_Voltage-Controlled_Amplifier.shtml [4] http://www.gearslutz.com/board/geekslutz-forum/67301-seeking-thats-2180-a.html Entry: SVF R/C for RC=10ms Date: Sat Nov 27 20:02:47 EST 2010 Type: tex \def\nF{\text{nF}} \def\uF{\mu\text{F}} \def\pF{\text{pF}} \def\ms{\text{ms}} \def\hz{\text{Hz}} \def\MO{\text{M}\Omega} \def\kO{\text{k}\Omega} For a SVF the corner frequency $f_0$ is at $(2\pi R C)^{-1}$. We're interested to take $f_0$ down to about $10$-$20\hz$. A time constant $\tau = RC$ of $10\ms$ would do it, which is at about $16\hz$. In a filter IC like MAX274[1] capacitors are on the small side (MAX274 has $80\pF$), which shows they are aimed at poles that are about $2$--$3$ orders of magnitude higher in frequency. The datasheet[2] mentions that $R_F > 10 \MO$ are best replaced with a T--network, which has some disadvantages. Doesn't look like these ICs are good for variable filters that go down to low frequencies. So what is a good way to pick the $R$ and $C$? With $R$ at $1\MO$, $C$ can be around $10\nF$. The DS1801[4] is $48\kO$, so I'm looking at $220\nF$ there. From what I gather you want the value of $C$ to be as low as possible while not making the value of $R$ too large to make it noise sensitive. The art of electronics[3] says to pick a round number capacitor in the vicinity of $C = 10/f_0 \uF$, which means an $R$ of about $10$--$20\kO$. Seems that digital pots are mostly in the $50\kO$ range so best design the manual filters around that value. I did find some EQ circuits that have $1\MO$ pots. Why so high? % [1] http://www.maxim-ic.com/datasheet/index.mvp/id/1452/t/al % [2] http://datasheets.maxim-ic.com/en/ds/MAX274-MAX275.pdf % [3] isbn://0521370957 % [4] http://www.maxim-ic.com/datasheet/index.mvp/id/2777 Entry: Transfer functions Date: Sun Nov 28 22:53:34 EST 2010 I was thinking that it might be an intersting exercise to write an impedance calculator in haskell, with bode plots, gui for interactive design. Then I'm thinking: what about spice? Entry: Transistor transconductance Date: Mon Nov 29 13:10:59 EST 2010 Type: tex If the point is to make a VCF with a little bit of a fat sound, it might be simplest to build it using transistors instead of opamps and VCAs or OTAs. The easiest way is to use current biasing $g_m$ for a common emitter configuration. Maybe it's time to go back to basics firsts. The tree transistor stages: \begin{itemize} \item Common emitter[1] for signal amplification. \item Common collector[2] or emitter follower for buffering. \item Common base[3] for high frequency operation (no Miller effect). \end{itemize} % [1] http://en.wikipedia.org/wiki/Common_emitter % [2] http://en.wikipedia.org/wiki/Common_collector % [3] http://en.wikipedia.org/wiki/Common_base Entry: LED power supply Date: Mon Nov 29 22:59:35 EST 2010 What kind of inductor is necessary to drive a bunch of LEDs (say 20-30) in a power efficient way? Variables: current determines wire gauge, inductance determines energy storage and thus switching frequency. At 20mA, 30 LEDs is 600mA. Entry: Diode ladder filter Date: Tue Nov 30 18:45:27 EST 2010 Type: tex I'm starting to get it. The small signal resistance of a diode depends on its bias current. The diode current is $I = I_0 \exp (V/V_T)$ where $V_T$ is a physical constant approximately equal to $23$mV at room temperature. The small signal conductance $S = 1/R$ is the derivative to $V$ or $S(I) = (1/V_T)I$ and thus $R(I) = V_T / I$. The small--signal ladder filter then becomes straightforward to analyze. The diodes act as resistors, and the circuit is fully symmetric which means each capacitor can be split into two parts with the middle connected to small--signal ground. The result is just a cascade of low pass R--C sections driven by a current source. The negative feedback loop completes the circuit, introducint resonance due to the positive feedback caused by the phase shift around the $RC$ frequency. Resistance decreases with increasing current, reducing $RC$ time constants and thus shifting poles to higher frequencies. Now, the transistor ladder filter is similar but it uses biased transistors instead of diodes. The transistors are in common base configuration\ldots % [1] http://www.timstinchcombe.co.uk/synth/diode_18_24/diode.html % [2] http://en.wikipedia.org/wiki/Diode_modelling % [3] http://en.wikipedia.org/wiki/Common_base Entry: R,C duality Date: Thu Dec 2 18:37:44 EST 2010 Type: tex Impedances and V,I duality seems straightforward. So what about the lowpass/highpass duality of RC networks? The difference is that R,C duality is about a different kind of transfer function. Impedances are current--to--voltage transfer functions while for the R,C duality the transfer function is voltage--to--voltage. Writing it out for a lowpass and highpass network we get $T_l = 1 / (1 + Z_R / Z_C)$ and $T_h = 1 / (1 + Z_C / Z_R)$. The duality maps $j\omega RC$ to its inverse. The main difference is that non--impedance transfer functions require a different operation: multiplication. Imedances just need addition and inversion, while a transfer function needs multiplication of impedance and admittance, so it seems fundamentally different. % [1] http://en.wikipedia.org/wiki/Duality_%28electrical_circuits%29 Entry: Modding the Behringer OD300 Date: Fri Dec 3 22:59:35 EST 2010 ( A Boss DS-2 clone. ) Playing with it a bit it seems that: - I need to build a DI with variable loading. The guitar is much less noisy when loaded with 10kOhm and I wonder if this is just due to the high-freq rolloff, or if there are other effects.. It seems to reduce hum. - It doesn't sound too bad straight into the UB1202 mixer. Capture this in a separate circuit. - For playing with the OD300 the full brightness is necessary, so no splitting off the signal and loading it on the mixer inputs. - The OD300 is alright. But it needs extra brightness. I have tone all the way up, and hi all the way up on the mixer. So, interesting mods: - Add a clean out after the OD300's input buffer. - More treble. It would be interesting to find out if the OD300 is really the Boss OD-2. I guess I could trace the circuit but I'm a bit lazy. From the DS-2 schematic it seems to be the "starved, discrete differential amp" circuit. Entry: JFET Transistors Date: Sun Dec 5 23:58:41 EST 2010 JFETs have two operating ranges: a linear region where they behave as a voltage controlled resistor, and a saturation region where they behave as current sources. Entry: Picking a staple transistor (BC549-BC559) Date: Mon Dec 6 02:47:38 EST 2010 EDIT: Starting from futurlec transistor value pack and what I find commented on http://www.diyaudio.com and http://www.diystompboxes.com What I want: to pick a single NPN-PNP transistor pair that's cheap and good enough for non-power audio apps. Needs high current gain (for input impedance), low noise for small signals/preamps. Not so important: bandwidth, max current/voltage/power. http://www.futurlec.com/TransGenSpec.shtml Transistor selection is still a bit of a mistery to me. What I do (think I) understand is this: - Bandwidth, not so important for audio - Noise, important for small signals - Current gain, important for input impedance of emitter follower - Max voltages, max power only really relevant for power amps. What I don't get: - Difference between switching, small signal, general purpose. - @Ic, collector cutoff current? (probably only for switching) - price: why is there such a huge difference (factor 50). This is what's in the value pack which contains the most popular transistors: http://www.futurlec.com/ValuePacks.shtml http://www.futurlec.com/TransGenBC.shtml 10 BC327 PNP 500mA 100-600 10 BC547 NPN 100mA 110-800 10 BC548 NPN 100mA 110-800 5 BC549 NPN 100mA LN 200-800 10 BC338 NPN 500mA 100-600 10 BC337 NPN 500mA 100-600 5 BC107 NPN 100mA 110-450 http://www.futurlec.com/TransGen2N.shtml http://www.classiccmp.org/rtellason/transistors-2n.html 10 2N2222 NPN SW 5 2N2907 PNP SW 5 C1815 NPN 5 C9013 NPN SS 5 C9012 PNP SS My summary of on-line search is this: (PNP / NPN) 2N5087 / 2N5089 for low-noise, general purpose BC560 / BC550 for low noise. C9012 / C9013 for small signal The latter are cheapest. I need to look at the datasheets to check these out. It's probably best to stick to one staple transistor and leave component optimization for a later stage. Sheets (internal refs) These are pretty thin. Cheap, current gain: 64-250 C9012 PNP md5://2a5fbc943ff0fd700f9db3501ca54cb7 C9013 NPN md5://0dcb0103571f86d446f01d20b5589683 More current gain: 400-1200 2N5087 PNP md5://6bc41770417204ff4953c15ec2fee282 2N5089 NPN md5://41bab55c79bf466d87189edd8e920003 Low noise: BC560 PNP md5://a4fb0b631e6d9a9016785126a73fce07 BC550 NPN md5://0a781a7c276c53cc2c1e77cac77f26ed Looks like BC559 / BC549 would also be ok, but 30V instead of 50V. They can probably take the place of anything I want to do so let's drop the the C9012/13 and 2N5087/89. Entry: Power supplies Date: Mon Dec 6 14:43:47 EST 2010 Time to get started. I see 2 reasonable options for power supplies: - 9V stompbox-style, possibly with 4.5V reference to facilitate opamp schematics. - 9V + 5V linear regulator for stompbox analog + uC digital. - 5V USB, possibly with some regulator to provide asymmetrical supply for low-power analog electronics, i.e. a MAX232[1]. - 5V USB + rail-to-rail single supply opamps (i.e. MAX494) [1] entry://20080901-172314 Entry: Opamp input Date: Mon Dec 6 20:07:59 EST 2010 What I see in many guitar effects input circuits - Input resistor R1 to ground 1M - Capacitor coupling, 1u - Resistor R2 100k to ground or 1/2 reference voltage The C is to bridge the DC difference between ground and the 1/2 ref. The R2 is necessary to make sure that C gets biased correctly if the input is zero volts, and R1 is for biasing the other end in case the source doesn't provide a DC path. Entry: Picking a staple OpAmp (TL072/TL074) Date: Mon Dec 6 20:38:33 EST 2010 EDIT: I'm picking TL072/TL074 for audio, which is old and definitely not best, but it's cheap and probably good enough. For other apps the cheapest LM358N/LM324N will do. Next to transistor selection, there is opamp selection. What I have in the box is this: - 6 x MAX494 $3.96 @1k quad, precision, low power, rail-to-rail, single supply +2.7V to +6V - 5 x MAX4167 $1.29 @1k dual, ..., high output drive These are Maxim samples, only useful for 5V operation, not the stomp-box 9V plan. Maybe I pick something simpler like - 2 x LM324N, quad, single/double 3V-32V (F: $0.25 0.22) - 3 x LM358N, dual, low power, single/double 3V-32V (F: $0.25 0.20) - 2 x TL072CN, dual, low noise, jfet, 36V (F: $0.25 0.22) - LM339N, comparator, $0.33 @ 1k From what I read[1] it seems that for cheap opamps, the LM358 isn't so good because it hass class-B output. The TL072CN is old and there are better opamps, but it's cheap and probably good enough for audio, so that's what I'm going to order. So conclusion: Audio: TL072/TL074 md5://e80e5dbb8b58ec9baced943a50902bca Non-audio low power: LM324N md5://26b5a7ca8fc97ad7258224f28fee102d LM358N md5://0903faac7d3137d58d30d6549adb0d17 [1] http://delicious.com/doelie/opamps Entry: Guitar output voltage and AC/DC coupling. Date: Tue Dec 7 13:55:04 EST 2010 Measuring both guitar and bass with DVM AC mV gives me just below 200mV max output. The quiet voltage is about 2.2mV which is probably hum due to the unshielded cable hookup (I have no scope yet...). So I think it's safe to conclude that guitar signals do not really need any boost when working with 9V or +- 4.5V circuits; the level is fine as it is. Next: Can a guitar be DC-coupled to the half-way ref voltage? This depends on the power supply use in other circuits. It seems to be the convention to tie the signal ground to negative power. In that case the ref voltage would be shorted. Answer: no, AC coupling is necessary. If box uses batteries (power supply is local) there is no problem. Next: What resistors should be used for a R/R voltage divider for the 1/2 ref voltage? Should there be a cap from ref to ground if there is a unity gain buffer? It seems the reason for the cap is to short AC noise to ground. Entry: Opamp Class A bias Date: Tue Dec 7 19:58:40 EST 2010 According to this thread[1] it's possible to run a class B opamp in class A by biasing current so that at all times only one of the transistors is conduction. This to eliminate cross-over distortion. This is mentioned in the LM358 data sheet under Application Hints. [1] http://www.electro-tech-online.com/general-electronics-chat/33505-biasing-op-amps-into-class.html Entry: Diode trick to prevent saturation Date: Tue Dec 7 20:24:27 EST 2010 Patent[1] : CLAMP CIRCUIT FOR PREVENTING SATURATION OF OPERATIONAL AMPLIFIER [1] http://www.freepatentsonline.com/3679989.html [2] http://www.diystompboxes.com/analogalchemy/sch/diodeopamp.html Entry: Distortion : Duty Cycle Date: Thu Dec 9 16:05:04 EST 2010 From [1]: "... if you filter properly, soft clip, and arrange for the duty cycle of the clipped signal to vary with varying signal levels, you get something very close to tube distortion." (John Murphy) Looking at the pictures, with a sine input, the varying duty cycle requires a-symmetrical clipping _and_ DC bias before entering the clipping network. The DC bias could be fed back from the average of the output, i.e. asymmetrical clipping of an AC-only sine wave leads to DC output, but adding proper DC bias to the input can make the output of the clipper DC free. Schematic: a typical inverting opamp with 1+2 asummetrical diode clipping, parallel gain resistor and possibly tone cap. Filter this output to get the DC component, i.e. f_c = 10 Hz, and feed this DC signal back into the circuit. Entry: Breadboarding duty cycle circuit (a-sym clip + DC feedback) Date: Sun Dec 12 21:06:33 EST 2010 This works as expected. Some notes: - Using 45x gain (100k / 2k2) to drive the diodes. - Used a 1N4148 // red led 1.87V. The led seems to have quite a large capacitance as it made the circuit less noisy. I tried with other led (a bit noisier) and 2 x 1N4148 (quite noisy). - Using 1M + 100n for DC, with 10k feedback (next to 2k2 guitar input). Using smaller feedback resistor gives more noise. Changing the 1M to 1k increases bass attenuation as expected. How to explain the value of the 10k feedback resistor? - Used a 4k7 pullup for the LM358N. At higher gain earlier I did see some severe crossover distortion which disappeared after adding a small enoug pullup resistor. To try / to do: - Make some EQs. - Figure out ways to get a smaller duty cycle. - Change the bias such that there is more headroom for the larger side. EDIT: changing the DC feedback resistor to 2k2 lowers the error signal. It probably also has some effect on the bandwidth, as some lower AC frequencies get fed in (RC network behaves as integrator at audio frequencies). Maybe the best thing is to make the resistor variable? Let's try again when the pots arrive. Entry: 2-Scroll circuit Date: Mon Dec 13 13:41:41 EST 2010 See [1]. The basic idea is to start with an unstable 2-pole filter (negative damping) implemented as an SVF. Then modify it such that one of the state variables can have a DC bias, which shifts the center point of the oscillation. Then a 3rd variable is introduced. This takes the function of "switch state". This can either be interpreted as binary, or as a 1-pole filtered binary state variable with a fast time constant. X,Y : unstable oscillator state variables X : biased state varible Z : "switch" state. This is a display of the X,Z plane. The idea is to bias the oscillator circuit in such a way that the unstable fixed point is at the "x" mark. Whenever the unstable oscillation crosses the comparator cut point, the state variable is switched which projects the point to the other plane, close to the unstable fixed point, where the oscillation starts to grow again. comparator cut / / --x---/--- ^ /| | / | |/ v --/---x--- / Z ^ | -- > X The variables: - unstable filter pole - unstable filter (negative) damping - switching speed - exact location of the `x' w.r.t. comparator cut line Questions: - Biquad instead of SVF? What we really want to control is the time it takes between state switches, independent of frequency. This is propertional to ring time, not Q. [1] ftp://ftp.esat.kuleuven.ac.be/pub/SISTA/suykens/reports/chaos_00_125.ps.gz Entry: DI box Date: Mon Dec 13 17:20:44 EST 2010 I'm building a simple DI box buffer/mixer. It reminds me again how far removed I am from being an experienced analog circuit designer ;) Goal: connect both bass and guitar to either a high-Z effects pedal input (trivial) or a low-Z mixer input (impedance +- 10k). Allow for cross fade mix. For the low-Z load, the main point is that the output impedance is resistive over the region of interest while say 50% voltage loss is not a problem. This means an output impedance of about 10k is enough; no need to go down to 1k. Input impedance needs to be high. This is straightforward: a 1M biasing resistor to 1/2 VCC ref and a large enough coupling cap. The 1/2 VCC ref can be a 100k/100k divider with 10uF buffer. The output was where I'm puzzled. Need to have both AC coupling to remove the 1/2 VCC bias. All the stomp box circuits I find online seem to be designed for high input impedance, judging from the couplings caps: 1uF on a 10kOhm input has a 3dB point of 15Hz. So, to be careful, let's pick 10uF coupling. This can come from the 10k linear mixing pot connecting the two buffer outputs. 10k buf1 o--/\/\/\/--o buf2 ^ | 10u 1k \---|(---x---/\/\/\---o out | / \ 100k / | x------------o | GND So, the 10u value is such that at a load of 10k, the impedance of the cap is small. At 20Hz this gives about 800 Ohm. The influence of the mixer pot isn't so important: it's just signal level attenuation (max 50% at 10k load). The 1k is there to prevent short circuit, and the 100k is there to bias the buffer capacitor at DC. Take-away lesson: the expected load impedance determines the size of the output coupling cap. Entry: MAX4167 Date: Mon Dec 13 18:59:00 EST 2010 Another design for a DI box, based on a low-voltage rail-to-rail MAXIM opamp MAX4167[1]. They do require +- 1.35V. Would they work from +- 1.2V? I'd like to run off of 2 AAA rechargables. Using 2 cells I can have a symmetrical supply. This significantly simplifies the circuit to the point of triviality, as no coupling caps are necessary. I used a small perfboard with a plastic socket. One of the channels works, the other one doesn't. All connections seem to check out fine, socket is fine too. Something's wrong that I don't see. EDIT: was just a bad solder joint. [1] http://www.maxim-ic.com/datasheet/index.mvp/id/1696 [2] md5://9558c480d31b252f521903d7bfc67275 Entry: The variable gain/resistor problem Date: Fri Dec 17 02:40:37 EST 2010 Looks like I'm out of luck. It's either the transistor/diode ladder or expensive or cumbersome chips (LM13700N dual ota @ $1.5 futurlec). Let's dig deeper. Why is variable gain so difficult? Because it's a multiplication, and we don't really have many multiplying components, so we use other tricks based on non-linear resistances and small signals: transistors and diodes and the exponential voltage/current transfer function. What about FETs? When the gate voltage is larger than both source and drain, it behaves as a variable resistor. How useful is this to build variable gain, variable time constant circuits? Entry: PWM resistor Date: Sat Dec 18 02:47:12 EST 2010 Found an idea on http://diystompboxes.com about using a pwm modulated analog switch to create a variable resistor using 2 series resistors, one bypassed. Considering the simplest case, there are 2 possibilities: series and parallel. The point is, how is the switching averaged out? I.e. PWM really needs a lowpass filter. In the series case, the filter would be an inductor, while in the parallel case it would be a capacitor. Hmm... doesn't it depend on what we want the resistor to do? I.e. is it a I->V or a V->I converter, meaning is it driven by a current or voltage source respectively. Entry: Peak squashing Date: Sun Dec 19 00:17:10 EST 2010 Thinking about the asymmetric peak squashing circuit (negative DC feedback after asymmetrical distortion). It should be possible to squash more to reduce peak level, instead of squashing the peaks on the other side. Trouble is, that doesn't really sound good. The 1N4148 + LED circuit with DC feedback sounds subtly different than without feedback, but more squashing introduces not so nice sounding distortion. Entry: Modular system Date: Sun Dec 19 20:21:10 EST 2010 So, make it easier to build effects, I need some kind of modular system. Doesn't need to be full-blown old school analog synth patch panel, just some cheap male + female headers. - All modules should provide buffered outputs - Allow for +- 10k input impedance (i.e. line inputs) Entry: Next step Date: Mon Dec 20 13:15:38 EST 2010 Playing a bit with basic electronics, the next step is to make that digitally controlled device. Rationale: the "analog" sound comes mostly from non-linearities in the signal chain, so you want signals that see any kind of nonlinear feedback to be analog. Control signals can probably be digital and "clean" linear filters, i.e. those that never see any clipping or other distortion, could probably be digitized also. About VCF: the simplest approach is to use BJT g_m biasing or diode small signal resistance to set filter poles. This requires temperature compensation, which could probably be done digitally too. Entry: Digitally compensated exponential converter Date: Mon Dec 20 14:16:15 EST 2010 How to control an analog synth digitally? What is the best design, assuming that we want to keep the signal path analog? * PROBLEM: Exponential-scale control is necessary for both amplitude and frequency somewhere in the control chain. The question is where to implement it? * FREE: BJTs cost about $0.02. Physically, the V_be vs I_c characteristic of a BJT is very near to exponential over a large current range, but it requires calibration due to the unknown curren scaling factor and junction temperature. At room temperature we have a scale of e / 26mV or 20mV per octave, which means standard 1V / octave needs about 50x voltage attenuatio.n * FREE: On-chip processing power is free. Even on tiny < $1 microcontrollers, since the control rate is so low. * NOT FREE: Digital to analog resolution. The cases that are readily available (PWM, delta-sigma or even ladder DA) all have linear error sensitivity, not exponential. * The cost of an analog exp converter is mostly the calibration: temperature compensation, trimpot component cost, manual (mechanical) setup cost. The collector current is mostly propertional to exp(V_BE/V_T) where V_T is the thermal voltage[1] equal to k T / q. The scaling factor depends on the circuit biasing. So, essentially, all things being equal, the voltage input that goes into a BJT based exponential converter has two parameters: scale (octaves per volt proportional to temperature) and offset, the biasing current of the network, determined by say 5% resistors. This affine transformation can be done in the digital domain. LM394N matched pair data sheet[2] contains some interesting "log/exp based application notes. A true linear-to-exponential converter schematic can be found in the National AN-30 application note[3]. Using a transistor array for temperature coupling, perform the following: - Factory mismatch calibration: determine whole function transfer: from D-A to controlled frequency and measure frequency (if separate). This takes care of controlling and measuring BJT differences. - On-line temperature calibration: measure output vs. feedback frequency. So, can it be built with only one transistor? The schematics I find all use a matched pair to get rid of the initial biasing problem, i.e. what current corresponds to 0V input. [1] http://en.wikipedia.org/wiki/Boltzmann_constant#Role_in_semiconductor_physics:_the_thermal_voltage [2] http://www.futurlec.com/Datasheet/Linear/LM394N.pdf [3] http://www.national.com/an/AN/AN-30.pdf Entry: Distortion board rev1 Date: Mon Dec 20 14:17:48 EST 2010 Board shortcomings: - No connectors or holes for in,out,GND,Vcc - No output coupling cap. - Feedback resistor hard to replace by pot. Also needs pot in series. - No feedback cap Bugs: - Diodes are the wrong way. Together with the biasing this made the opamp saturate. Fix: replace 100k R5 with 22k to bring the bias point near 1/2 Vcc. - Schematics wrong: the 2nd opamp is a ground following buffer ;) - After different biasing, 10K from out to ground is necessary to enable class A, only upper transistor in LM358. - 1/2 ref needs regulation. Entry: Futurlec transistor arrays Date: Mon Dec 20 19:00:49 EST 2010 What am I looking for? - Thermal matching. - One transistor free for on-line calibration feedback - One (automated) factory run for calibrating other circuit parameters, i.e. resistors. Only checking through-hole components, what's the cheapest usable transistor array? MC1413 - Darlington Transistor Array 7 $0.28 [1] CA3046N - NPN Transistor Array 2D+3 $0.80 [2] CA3086N - Transistor Array NPN 2D+3 $0.79 [3] LM3046N - Transistor Array 2D+3 $1.10 [4] The cheapest one, MC1413[1] are 7 NPN darlingtons, common emitter. I'm not sure if those are very useful. The other 3 are clones: 2 differential NPN + 3 NPN, fully accessible. [1] http://www.futurlec.com/Datasheet/Linear/MC1413.pdf [2] http://www.futurlec.com/Datasheet/Linear/CA3046N.pdf [3] http://www.futurlec.com/Datasheet/Linear/CA3086N.pdf [4] http://www.futurlec.com/Datasheet/Linear/LM3046.pdf Entry: 1-pole ripple: PWM vs SD Date: Mon Dec 20 19:49:14 EST 2010 I'm thinking: SD has higher frequency close to its 1/2 level and is thuis "naturally non-linear" in noise. However, it might exhibit low-frequency periodicity, which needs to be eliminated. TODO: make this more quantifiable. Entry: Inductors for LED driver Date: Tue Dec 21 23:20:22 EST 2010 I got the 470,1000,2200 uH power inductors from Futurlec in the mail today. Seems their series resistance is 1,2,4 Ohm respectively, which means I can't do much with them for driving the LED lamp at its low voltage, which has 14 white LEDs in parallel. The idea seems to be to use these for larger voltages. Series LED circuit seems more appropriate. This then allows a boost converter[1]. * The current will be lower (order of 20mA instead of 300mA for 15 LEDs). This is good for efficiency. * However, the charge cycle will take proportionally longer than the discharge. This means the LEDs are pulsed with a short duty cycle and thus need larger currents. This seems to be a case of the law of conservation of misery. Maybe I postpone this until I have some more info. It seems that using smaller inductors and higher switching speed is a good way to go. With this information, it seems that higher efficiency is not really going to be one of the properties of the controller, compared to the 1Ohm series resistor I have now. However, what can be useful is the output current regulation when battery voltage drops, and the possibility to regulate the intensity. Again, what are the variables: - Output voltage, current (LED topology + dimmer) - Switch frequency - Inductance - Series resistance Higher inductance, lower switching frequency. There seems to be no real disadvantage to high frequency apart from switching losses, which are (I believe) mostly due to transistor speed and capacitive load. The higher the inductance, the higher the resitance (for the same inductor size). Is there any advantage for higher inductances? This[3] might be an interesting place to look. [1] http://en.wikipedia.org/wiki/Boost_converter [2] entry://20101216-004450 [3] http://www.coilcraft.com/led.cfm Entry: SVF dual antilog pots Date: Wed Dec 22 21:20:56 EST 2010 These seem to be hard to find and expensive. It might be best to just make the circuit itself more complicated, adding voltage control. I have dual log pots, 50K which should be fine to do some experiments. EDIT: tried the basic SVF and it oscillates for higher frequencies. Possible problems: impedance of input resistor gets too low (50k pot). Entry: Pot tapering - does it actually work? Date: Wed Dec 22 22:00:23 EST 2010 Context: the problem is that it's hard to obtain dual-gang reverse log pots for frequency control, but the linear parts are easier to get. In ``The secret life of pots'' [1] it is explained how to create different voltage divider or resistance curves based on placing resistors in parallel with wiper and end. How wel does this work? And more importantly, what do the pots I can (would) actually buy look like? It all depends on the application, right? Making a 20Hz to 20kHz RC oscillator requires the middle position to have the geometric mean of sqrt(1000) = +- 30. This seems pretty steep to do with the parallel resistor trick. I wonder how good the tapers are for the log pots I got from Futurlec. They give a 1/2 resistance of 13% or about 1/8, and they do seem to have a dual-linear range with a knee at 12k for the 50k pot. [1] http://www.geofex.com/article_folders/potsecrets/potscret.htm Entry: OTA nonlinearity Date: Thu Dec 23 13:32:10 EST 2010 It appears that the input nonlinearity of an OTA is quite essential to the characteristic sound of analog filters, especially near high gain or high resonance settings, where it provides a graceful compression. An OTA is essentially a differential pair with a mirrored current load, leaving an output path for the difference current. With the current output open circuit, or loaded with a very high output impedance, it acts as a high gain voltage amplifier where the output current is loaded by the active current source load's output impedance. When an OTA (high output impedance) is followed by a buffer it is essentially an opamp: a high gain differential voltage amplifier. Opamps are exclusively used in closed loop circuits, where the input voltage difference is usually small (ideally 0V). OTAs are mostly used open loop, so the input nonlinearity is significant. It would be interesting to investigate the effect of transistor V_BE mismatch for both the input pair and the current mirror pair. Entry: Transistor matcher Date: Thu Dec 23 15:00:39 EST 2010 Matching transistors for differential pairs and current mirrors is not about matching current gain, but about matching the voltage to current curve, which corresponds to matching the reverse saturation current of the base–emitter diode in the Ebers-Moll model. The Moog guideline for matching[1] is to match V_BE to 1mV for 100uA. This is a current mismatch of e^(1mV/26mV) wich is 4% relative current mismatch. So it seems a higher matching accuracy is possible by measuring the current difference directly, i.e. to use a one-to-many current mirror array. With high current gain transistors and 4% current matching, the effect of the double base current in the controlling leg is negligible. Can probably be microcontrolled. Would need calibration of the resistor values used to measure the current. [1] http://www.fantasyjackpalance.com/fjp/sound/synth/synthdata/16-minimoog/002/905-matching-transistor.gif Entry: OTA mismatch: diff pair + current mirror Date: Thu Dec 23 15:37:56 EST 2010 An OTA needs two matched pairs: the differential input pair and the active load current mirror pair. The effect of mismatch is DIFF PAIR: input offset voltage. CURRENT MIRROR: fixed current ratio between 2 legs. The CMMR comes from the emittor resistor, which is large if a current source is used, and mismatch doesn't enter the picture here. See Early effect[1]. So what is the effect of these the current mirror mismatch? Is it also just offset? The current ratio in the two legs is proportional to exp(V1-V2 / V_T). In the case where the current mirror has a mismatch current ration a, and the output current is zero, the mismatch is carried by a _fixed_ voltage offset between the two inputs. Does this matter at all when we AC-couple the input and provide proper DC biasing? What is the real disadvantage of DC offset for audio applications? ( Context: can we compensate for mismatch without having to perform component selection? Matched pairs are expensive, though there are some cheap FET SMT ones: FDG6303N is $7 in 3000 volumes ). [1] http://en.wikipedia.org/wiki/Early_effect Entry: Questions Date: Thu Dec 23 21:46:13 EST 2010 - Is offset the only problem for LTP (Long Tail Pair) ? - LTP offset for opamp / OTA: does it really matter for non-DC audio? Note that current gain in an ideal OTA is I_out = I_bias exp(V_d / V_T). Since V_T is 25mV, you do want to take it into account when DC coupling is used and mismatch goes over a couple of mV. Entry: OTA output current mirrors Date: Fri Dec 24 00:10:36 EST 2010 One things I got wrong is the use of two current mirrors that take the current from the two differential pair legs and bring it out. See explanation and CA3080 schematic here[1]. The schematic I'm working with is the differential pair with current mirror load [2], and the discrete 4-pole filter [3] (which has the PNP's upside down in the schematic).. So what's the difference? Why the two extra current mirrors? The answer is probably to remove the dependency on the common mode voltage. I.e. if that's high, the differential pair resistors might saturate trying to provide a low output voltage. However, if by design this isn't a problem (as in the 4-pole filter?) the current mirror can be left out. [1] http://www.uni-bonn.de/~uzs159/ota3080.html [2] http://en.wikipedia.org/wiki/Long_tailed_pair#Long-tailed_pair [3] http://www.jhaible.de/tonline_stuff/jh2040.gif Entry: Simpler discrete SVF Date: Fri Dec 24 00:20:46 EST 2010 So, what about building an SVF without (discrete) OTAs but using single-ended common emitter stages instead? Writing down some obvious (ly wrong) circuits it seems that biasing this isn't so easy. There seems to be a tradeoff replacing transistors with resistors and caps. Question: how do you bias an active load common emitter circuit? Entry: Exponential converter Date: Fri Dec 24 01:36:27 EST 2010 The circuit in Figure 3 [1] can be simplified by removing A2 and using the collector current of Q2 as the output to set the bias current of a differential pair, or in reverse polarity, to drive the current input of an OTA. ( The circuit can be simplified a great deal by removing the capacitors and input and output resistors that don't seem to be necessary for a modern opamp. They are not mentioned in the AN either. Note, this is dated November 1969! ) Note that this circuit is really just a differential pair where one of the inputs is at ground, and the total setup current is regulated such that the current in one of the legs remains constant. The baseline is: I1 / I2 = exp[(V1 - V2) / V_T] This circuit computes a negative exponential (current reduces as voltage rises). It can easily be inverted by swapping the inputs. However it seems simplest to keep it as is, since that allows for multiple current mirroring transistors to be driven. The circuit in [2] also has C2 and R4 from [3], figure 3. Maybe C2 is necessary to compensate the feedback loop for higher frequencies. I don't get R4 though. It seems to limit the output impedance. Anyway, this circuit has two inputs: input CV and reference voltage wich sets the 0 current. This gives enough information to perform calibration. [1] http://www.national.com/an/AN/AN-30.pdf [2] http://www.jhaible.de/tonline_stuff/jh2040.gif Entry: SVF time constants Date: Fri Dec 24 02:07:40 EST 2010 It's ok if the time constants in both sections differ a bit. It's their geometric mean that counts. If both are set by the same biasing current there should be no problem. Entry: PIC-controlled hybrid synth Date: Fri Dec 24 02:15:18 EST 2010 So it looks like I have most components to make the controller: - Diode ladder filter or SVF - 2 x Digitallty controlled exponential converter: linear reference and exponential control inputs, one each for: - filter cutoff - analog sawtooth generator (could use frequency feedback) Components (ladder): * 2 x matched NPN pair * Opamps (couple for feedback too) * 8 x diode, 4 x cap Components (SVF) * LM13700 * 3 x matched PNP (3-legged exponential converter) * Opamps or transistors for buffers. Entry: PWM expo Date: Fri Dec 24 12:07:00 EST 2010 Next problem: how does a RC filtered pwm interact with an exponential converter? Should the output be filtered too? The real question is: is there some form of modulation that will be optimal in some form? It seems to me that the most important property is not that the error signal is small, but that it is free of audible patterns. I already have 2 that are not so optimal: - PWM: pretty clear period ;) However this should work if the modulation frequency is well above 20kHz. - integrating SD: advantage: frequency is very high in the mid-range, which might be ok for audio as that's where we're most sensitive. What are the numbers? I think the PIC can do 100ns PWM resolution. That gives 500 slots in a 20kHz wave. That's not enough resolution. Probably need between 10 to 100 times more, so it looks like some decorrelation is necessary. About SD: how much of the dynamic range do you need to give up to not run into degenerate cases with very small duty cycle, and long period? Is it possible to temporally "rearrange" a binary wave form in a cheap way, i.e. random transpositions. See dithered PWM. Entry: Dithered PWM Date: Sat Dec 25 01:45:59 EST 2010 Probaly re-inventing something, but the idea is this: instead of sending out a minimal switching varying duty cycle pulse wave, send out a _permuted_ version, and change the permutation on each duty cycle. This shouln't be too difficult when using an easy to compute permutation, i.e. an LFSR. For an LFSR it works like this: generate the sequence in the usual way as n-bit numbers, and send out the carry result of comparing to the desired output signal average. For the next cycle, switch polynomials, or even just start at a different inital point. Anything that's cheap such that the next period and the previous one are not correlated. This really should work. How fast can it be implemented on a PIC? Is it actually better than simply using dithered sigma/delta? Entry: Combinations of dithered Sigma/Delta and PWM. Date: Sat Dec 25 02:15:39 EST 2010 Thinking about it a bit more, the problem isn't really periodicities in the inaudible part over 20kHz: PWM can be used there. What is needed is decorrelation of the audible part. Stacking a dithering sigma delta modulator on top of a PWM would also solve the speed problem, as the PWM can be offloaded to hardware while the compute intensive parts can be performed at a lower frequency. Numbers: Suppose we pick a PWM frequency of 10 MHz / 256, which is about 40kHz. That gives 8 bits precision on level 1. Level 2 could then add 8 or even 16 bits more, and has a bit less than 256 cycles to perform the calculation. I.e at 152 Hz we have 16 bits precision, and at 2 second time scale we have 24, depending on the time scale of the following filters. Probably don't need that much. Main goal however is to have more than one output. Ideally all of the pins should be usable as modulated outputs. Dithering can probably be reused for all channels and performing all the calculations in 256 cycles seems doable, say 16 cyles per channel. The problem is how to do the switching itself. One possible way to make it implementable is to allow some slack in the output that feeds back into the 2nd layer. I.e. let's say we try to make the PWM exact, but always measure the timing register of the output pin transition. This should make it possible to spread out the transitions so they can be done sequentially, but it does requires sorting of the transition times. This seems like an interesting idea but can it be made to work? The "apparent" non-determinism worries me. But the general idea seems to be solid. Problem: The "large cycle" problem also appears here if the output is close to the PWM scale crossing. Maybe this should use some form of overlaying, such that the SD is only used in 1/2 of its dynamic range. I.e. loose 1 bit to limit the cycles to period 4. Entry: PIC comparator output Date: Sat Dec 25 03:06:52 EST 2010 For the current-source controlled sawtooth generator I need a comparator on the PIC with output to the discharge transistor. The 18F1220 doesn't have on-board comparators. It's not a disaster to use an off-board one as there might be some other uses for a quad comparator chip, but let's look at the next one up: the 18F2550 has two, both have (invertable) digital outputs C1OUT/C2OUT. Entry: Current to frequency converter Date: Sat Dec 25 03:23:05 EST 2010 Instead of putting a resistor in series with a current source, it's also possible to put a sawtooth generator (capacitor, comparator, discharge tor) and use its pulse output frequency as measurement. This allows large dynamic range for a fixed voltage span. Entry: 1/2 range Sigma Delta Date: Sat Dec 25 03:43:12 EST 2010 Maybe it's best to simply always do this: if switching between 0 and 1, never use the range outside of [1/4, 3/4]. This avoids large period cycles as it places the max at 4 time units. To combine this with a low-level PWM we could use the low bit of the PWM to "center" the SD stage such that it operates in 1/2 range. I.e. for an output around 3 it could switch between 2 and 4, while for an output around 4 it could switch between 3 and 5. Entry: PWM/SD and clock jitter Date: Sat Dec 25 12:53:08 EST 2010 I'm not sure if I need to worry a lot about this. Anyways, this document by Bob Adams (Analog Devices) [1] is an interesting read about current technology. Especially the part about class D amps is quite relevant. The whole workshop[2] seems quite interesting: While high oversampling is a preferred technology in digital signal encoding, the advantages of redundancy are far from clearly understood. Single bit quantization schemes such as Sigma-Delta Modulation are intimately connected with number theory, dynamical systems, and stochastic processes. These methods are also used in other applications such as halftoning. The workshop will bring together selected experts, from a variety of scientific disciplines, whose work interfaces coarse quantization techniques. The focus of the workshop will be to explain the benefits of redundancy in this setting and to describe the compelling open problems. [1] http://www.cscamm.umd.edu/programs/ocq05/adams/adams_ocq05.pdf [2] http://www.cscamm.umd.edu/programs/ocq05/ Entry: CD4049UBE current mirror Date: Sun Dec 26 00:41:52 EST 2010 Is it useful to use a CD4049UBE as a matched differential pair or current mirror? Not as differential pair as the correct leads are not available, but a current mirror maybe? In [2] some interesting things are mentioned: - The well-known distortion effects. - Some Fairchild application notes. - "Datong Clipper"[3], which modulates up the sound, clips, then modulates down. This makes sure all the harmonics are up. [1] http://www.electronicskb.com/Uwe/Forum.aspx/design/6079/Analog-use-of-CMOS-logic-chips [2] entry://20101217-001132 [3] http://myweb.tiscali.co.uk/david.brewerton/DatongRFC.pdf Entry: State variable filter Date: Sun Dec 26 02:36:01 EST 2010 I have one breadboarded, but intuition is missing. - What is the influence of the 2 integrator feedback coefficient? - How to prevent small resistors = large opamp loads? See TAOE[1] p 279 which advises to keep resistors above 5k. - What about the open loop gain at a particular frequency? The time constant is set by the RC product, but the gain at a particular frequency is not. - Why does the SVF oscillate? An ideal one is not supposed to. Is this due to noise or nonlinearities? [1] isbn://0521370957 Entry: Current conversion, frequency feedback Date: Sun Dec 26 13:10:45 EST 2010 Problem: building a lin -> exp converter to be used in an oscillator requires temperature stabilization. It might be simplest to do this closed-loop. However, this requires a large resolution. The only large resolution available on a cheap uC is time, so it might be a good idea to convert the output current to a variable frequency circuit: i.e. to add a relaxation oscillator to each exp output circuit. Questions: - The exp converter current is most likely used to set the bias current in a differential pair. How much voltage can we use and does this feed through to the signal (CMRR?). Entry: Next analog experiment Date: Thu Dec 30 21:29:57 EST 2010 The SVF works fine with the Q feedback connected, though it doesn't oscillate at low frequencies and Q=inf. Next: the CD4049UBE as a variable resistor. What can I expect? Entry: FETs Date: Fri Dec 31 00:25:04 EST 2010 After the fear of opamps and the fear of BJT, now the fear of FETs. - JFET, V_T < 0. Does this mean that it is really only useful as an amplifier, biased in the saturated region? - When does saturation start? - What about using a JFET as a switch, as I've found in many guitar pedals. These have signals biased at 4.5V so there is some room to get the gate voltage low to turn off the switch. - V_T seems to have quite some spread: * 2N5457 -0.5 to -6.0 * 2N5484 -0.3 to -3.0 From the CD4049UBE hex CMOS inverter datasheet the voltage transfer graph also displays similar spread. See page 123 of TAOE. Accorting to that it's about 2V for MOSFETs and 5V for JFET. Compare to 0.63V - 0.83V for BJT (200mV), with 50mV typical. ( So I guess the JFET input TL071 also has high offset. Yep. 13mV max vs 3 mV max for LM324 ) How do you design with that? Some notes about linearizing resistance[1]. See also TAOE p139. In TAOE the summary is made. When to use FETS? - High impedance, low current - Voltage controlled resistor (VCR) - Voltage controlled current source (VCCS) - Analog switches - Power switching - Digital logic [1] http://freespace.virgin.net/ljmayes.mal/comp/vcr.htm Entry: Staple FETs Date: Fri Dec 31 13:01:35 EST 2010 Going from what I find online and checking with Futurlec pricing. Seems these should work: - nMOSFET 2N7002 (7c) or 2M7000 (10c) - nJFET 2N5485 (10c) The 2N5484 (80c) / 2N5485 (90c) nJFET are a lot more expensive. What's their main advantage? Datasheet says high speed switching / RF. Why would that be necessary for audio? Then power FETs. Goal is to get to +- 300W switching apps (1/2 hp). Maybe it's simpler to buy an inverter and modify it, or take apart some PC power supplies. Price range on Tayda for VA +- 100W is about $0.5 - $2. Parameters of interest for switching are mostly max voltage and max current. There are different ratios trading max current for max voltage. Not for now. Entry: Staapl test circuit Date: Fri Dec 31 13:47:05 EST 2010 Main goal: test the Staapl s-expression interface + get an 18F hooked up to the experiment board. issues to solve: - voltage regulator - standard mapping of USB TTY ports on zoo I have one 18F2620 @ 40Mhz board that's not used, and it uses the old 6x1 header as opposed to the "zwizwa standard" 5x2 header. This one could be used for debug purpose only. Next: how to associate a particular USB device to a particular tty? Entry: Diode ladder chirps Date: Sat Jan 1 01:21:29 EST 2011 According to [1], the chirpiness is a well-known feature of the 303, and in the x0xb0x there's a special transistor SA733P[3] that's supposed to cause that sound. Hmm... Reminds me of fuzz GaAs voodoo. Apparently[3] it's due to higher current gain, which makes sense. Also, the warble in the resonnance is caused by power supply fluctuations. However the module he's playing (Oakley sound super ladder filter [2]) doesn't have special transistors and has the chirpiness anyway. Doesn't make a lot of sense. Another things he mentions is the 1-pole filter on the 303. What's that about? Looks like there are more "varislope" or "variable slope" filters around. Check online. [1] http://www.youtube.com/watch?v=kxiHEJ_24FA [2] http://www.oakleysound.com/super-d.htm [3] http://www.ladyada.net/make/x0xb0x/mods.html Entry: SVF experiments Date: Sat Jan 1 12:51:01 EST 2011 Been playing a bit more. Some conclusions: - Limiting diodes in parallel with the integrator capacitors works well to keep the self-oscillation in check. Leaving saturation to the opamp doesn't seem to be a good idea. - Don't use LM324 for audio. The crossover distortion is quite severe, and it doesn't really pay to bias each stage into class A. - The feedback through the 2 integrating sections requires an inverting amplifier. The gain of this section is essentially free, and can be used to shift the poles. Higher gain gives higher frequencies. This is useful for picking lower capacitor values in case the input resistor for the integrators has a low values. - Negative Q. Adding a slight amount of positive feedback after the first integrator allows for self osc over the full frequency range. With the straightforward (positive) Q I don't get to self-osc in the lower frequencies. The inverter is unit gain with 100k / 100k, so I've added a 1M negative feedback resistor adding 1/10 to the [0,1] range provided by the voltage divider negative feedback. - HF Oscillations: I have about 1MHz oscillation going on. ( It's gone now, might be breadboard fluke. ) - The self-osc is nice though. Especially how large low frequency inputs "squash" a higher frequency oscillation. That aphex twin sound. It's fun to play with, but the really interesting thing about filters is when they are time varying (and nonlinear). Entry: Minimal digital processing setup Date: Sat Jan 1 15:07:48 EST 2011 What does a digital EQ cost in components? The processing itself is probably cheap, but the anti-aliasing and reconstruction doesn't seem to be. For building circuits with multiple A <-> D conversions a better approach is necessary. This probably requires programmable logic. It is possible to do fairly decent sigma/delta SD and class D D/A on an FPGA with very simple external circuits. For uC circuits I'm afraid that there isn't enough serial speed to pull this off in an efficient way (i.e. multiple channels). Entry: The integrating AD Date: Sat Jan 1 15:18:14 EST 2011 In order to minimize aliasing it is sometimes useful to employ integrating A/D converters. Chuck more's chip use an interesting V to F converter to implement this[1]. I wonder how this is done in commercial integrating A/D chips. [1] http://www.colorforth.com/immunity.htm Entry: Synth: the real problem Date: Sat Jan 1 15:44:35 EST 2011 After doing some experiments with analog circuits, I am now convinced that the only real problem is the D/A conversion for the control signals. For A/D (controller feedback measurements) there is the PIC's A/D convertor, and digital frequency measurement (timer, counter). I suppose these are going to be good enough, as they are mostly needed for low time-scale measurements, i.e. oscillator stability. The question is: will D/A errors be audible? My huch is that: yes, they will be audible, but we want them to sound random. I.e. random pitch fluctuations are not so problematic, and might even sound good. The next thing to do might then be to perform some analytical tests. Given 1-pole filtering, what does the noise sound like? Roadmap: - Build a real modulator (i.e. dithered S/D) and _listen_ to the noise ripple, i.e. when generating a ramp signal: * does the noise sound white? * does the noise change when the D/A steps up? - Use this to modulate an oscillator, i.e. an exp-converter -> 555 sawtooth generator. - Build an analytical model and perform some randomness tests. Entry: Co-design Date: Sun Jan 2 14:47:51 EST 2011 This is what I've learned from my experience with the modem late 2007: * Don't build any DSP application without a model. * Focus on translation of the model to implementation, preserving correctness. While dealing with the nitty gritty low-level optimizations, it's too easy to mess up correctness in subtle ways. So let's put that to the test. The goal is to write a noise-shaping sigma-delta modulator / class D amplifier, using as much as possible the hardware features of the PIC. Entry: Gilbert cell multiplier Date: Sun Jan 2 20:32:01 EST 2011 [1] http://www.analog.com/static/imported-files/tutorials/MT-079.pdf [2] http://en.wikipedia.org/wiki/Gilbert_cell [3] http://en.wikipedia.org/wiki/Translinear_circuit [4] entry://../electronics/20110118-232509 [5] http://www.sadt.com/faq.html Entry: Class D / Sigma Delta lit Date: Mon Jan 3 00:09:52 EST 2011 Where can I find informaton about S/D modulation. Starting from [1] I found the name Gabor C. Temes[3]. The book [2] seems nice. [1] http://www.scalatech.co.uk/papers/jaes496.pdf [2] isbn://0780310454 [3] http://eecs.oregonstate.edu/research/members/temes/index.html Entry: The simple 1-st order SD Date: Mon Jan 3 00:59:29 EST 2011 Some BOEC: With a 1st order SD the noise is going to have a 1st order highpass spectrum, with a 1st order lowpass reconstruction filter we get a shelving filter with flat noise spectrum. The noise floor is then directly proportional to the oversampling factor at the 3db point of the lowpass filter. I really need to simulate this.. I think I'm understimating the power of the noise. Entry: Simple headphone guitar amp Date: Mon Jan 3 19:57:20 EST 2011 Since I have plenty of low voltage rail-to-rail MAX4167 dual / MAX494 quad amps that work off of +- 1.2V it might be interesting to build a headphone amp, as it's quite trivial: 1 non-inverting opamp has both high input impedance and low output impedance. The only thing to find out is how much gain it should have. Probably not too much. The unity gain box I have already gives a reasonable amount of signal on the Sennheiser HD457 headphones. Seems that 10x should be plenty. I might even have separate drive and level pots. Nah let's keep it simple. If it buffers properly then it's easy to add external effects. What about 1M input pot and a 10x fixed gain? Entry: The analog synth myths Date: Tue Jan 4 03:02:06 EST 2011 The consensus amongst electronics musicians that use analog gear seems to be that it is "impossible" to replace with digital simulations. Why is that? * High frequencies: discontinuous waveforms (square, saw) and signal envelopes contain very high frequencies that are hard to reproduce digitally. Essentially there is only one trick: generate and process with high sample rate and downconvert. * Subtle and less subtle nonlinearities. The characteristic sound of an analog filter is due to many "second order" effects, i.e. transistor non-linearities, signal modulations due to power supply coupling, ... Basically I don't buy this "impossible" business. Though it might be prohibitively expensive to simulate analog gear up to the point where the simulation becomes undistinguishable from the real deal. But, going all the way of simulating circuits opens up a whole spectrum of modifications that are physically not possible. Entry: Simply dirty exponential converter Date: Wed Jan 5 08:30:41 EST 2011 As mentioned by Gert, it might be possible to do it "simply, dirty" by driving the base of a BJT directly, and solve the rest with the (digital) feedback controller. My concern is then to at least make it safe enough so we don't blow up the BJT due to controller bugs. Let's analyze this minimalistic circuit: I_out RL o----/\/\/\---o Vcc | R / o---/\/\/\/----o----|/ Q (i.e. 2n3904 NPN) | |\ | V PWM in C ===== | | | | | o--------------o------o GND * Safety For safety there needs to be an R between the PWM drive and the base of Q. If PWM gets stuck high, R will limit the current once C is charged. * Filter The 3dB point should probably be set around 200Hz. At 10MHz PIC clock resolution this gives 50000x oversampling, or a little over 15 bits of binary modulation resolution. * PWM levels The useful voltage range at the base of Q is determined by the dynamic range of the current. We need about 4 decades which corresponds to roughly 10 V_T or about 250mV. V_BE at max current is around 600-700 mV. The useful control range at the base will thus be about 300-700mV. Allowing for some modulation headroom to get sufficiently fast rise times, it seems that PWM levels of 0-1V are going to be optimal. * Impedance RC product is fixed by bandwidth constraints, so what remains is to pick the impedance or the R/C ratio. The impedance of the filter circuit needs to be relatively high because it needs to drive the transistor base current I_BE. There are two ways of looking at this: C needs to be large wrt I_BE such that voltage drop due to I_BE should be much less than the expected ripple introduced by the load/unload currents. Alternatively one can say that the leak current due to I_BE should be much less than the load/unload currents, leading to small R. In any case: this load current is signal-dependent, so it needs to either be completely eliminated through low R and C impedance, or we need a compensation to deal with this nonlinearity on the fly. This compensation needs to be fast relative to the speed at which human hearing can detect de-tuning. I'd say about 100-200ms for a stable tone. It seems C needs to be as high as possible as it needs to drive the transistor base current. This load is nonlinear so we probably best keep its effects minimal in order to keep the PWM->V_BE transfer average as linear as possible. If C is large R needs to be relatively small. R's low bound is set by a safety limit determined by the max current setting. Max I_BE is determined by the load of Q (say order 1mA) over Q's current gain, which can be highly variable. * R_L Determined by max current output, probably around 1mA. This is for test only: in operation the load will be an emitter coupled pair or an OTA input (requires PNP version of above schematic). * Current filtering? It might be necessary to filter the current ripple using a small inductor at the collector of Q. This to prevent "peaked" current wave forms due to the exponential conversion. However, when the voltage ripple at the base is small, the AC transfer function is fairly linear and the output ripple's wave shape should resemble the input, which will be +- triangular. * Eliminate PWM reference? As mentioned above, PWM needs only 0-1V, so driving from 0-5V is mostly a waste of dynamic range. However, driving from anything else than Vcc requires switching circuitry that significantly complicates the circuit. I don't think the cheap buffer/inverter chips operate from a 1V supply. What about this hack: use 2 PIC pins attached to the buffer cap through 2 different resistors: one used for charge and one for discharge. Picking a larger resistor for the "more distant" rail should make it possible to keep the rise times equal in the range of interest. Say R_5V = 5 x R_0V. Instead of charging / discharging through 2 different resistors, we could also discharge through 2 resistors in parallel and charge through one. When more pins are available, this could also be used to use some different rise/fall time configurations. Problem: the transfer is then no longer simply an RC filter. My hunch is that it will be fine as long as you stay away far enough from the rails. At some DC point, the 2 resistors act as current sources / sinks. However, this analysis is signal-dependent so introduces some nonlinearity in the transfer function that is measurable. Overall this nonlinearity does seem predictable and probably can be compensated once when the exact resistance values and cap value are known. * Feedback This circuit is sensitive to the following disturbances, sorted from low to high variation over time. - Manufacturing spread due to V_BE spread and Q's current gain. In theory this could be calibrated once. - Temperature drift: mostly 1st order during startup, after that it might be signal dependent if there's not enough thermal mass attached to the transistors. All things equal, output current varies 20% over 50 degrees variation in die temperature. - Non-linearities in the control loop from duty cycle to V_BE. These are due to input bias current, the 2-resistor trick, and possibly transistor nonlearities (probably small). This needs fast response in the order of 100ms, i.e. the time necessary for the ear to figure out an oscillator is not tuned correctly. Bottom line: it's quite useless without compensation. What measurements can or can't be used? * Due to the high dynamic range of the output current, we can't use current measuring resistors for feedback. ADC resolution is too low. * We can use timing-based feedback derived from an oscillator. This can go to arbitrary high resolution by averaging capture times of oscillator transitions fed into the PIC over longer time scales. Note that we could use thermally coupled (and possibly V_BE matched) transistors to use one for driving the circuit and one for driving the feedback oscillator in case the circuit doesn't implement an oscillator but i.e. a filter or an envelope. * We can measure V_BE at 12 bits resolution, which should be enough for compensating the curved response, but of course doesn't solve V_BE spread or thermal drift. It seems best to split compensation into two parts: * Between runs, or once after manufacturing, we can store the compensation point in ROM. This should capture the large but relatively constant variation due to component spread and aging. * The temperature spread can then be tracked on-line at a rate of say 1 update per second. Nonlinearities can also be compensated this way, but this requires a tighter control loop. In general it seems better to aim for a tighter control loop that can capture both temperature variations and control chain non-linearities, than to design a laxer control loop and use feedforward calibration. The former might relax some more high-frequency timing issues in the pulse modulator. Caveat: using frequency-feedback necessarily introduces a large delay in the feedback loop. This might introduce instabiltities. * Oscillator A bare bones sawtooth oscillator can be constructed from this circuit by * Numbers Starting point: I_out max 1mA. Everything else scales with this. Designing for PWM voltage of 1V. Using 2N3904[1]. I'm not sure what to pick for nominal h_fe but let's use 100. Data sheet range is 40-300 over the useful range. With 100, max I_BE is then 10mA. Might need a different transistor with higher current gain. Scale design accordingly. [1] http://www.fairchildsemi.com/ds/2N/2N3904.pdf Entry: Compensated Sawtooth Oscillator Date: Thu Jan 6 11:19:38 EST 2011 Moving forward from [1]. The absolute bare-bones circuit for a sawtooth oscollator with exponential current drive is something like this: --o-- Vcc | | ===== C2 | TRIG/ o------------------o V_out DISCH | R1 / PWM o---/\/\/\/--o---|/ Q1 (i.e. 2n3904 NPN) | |\ | V C1 ===== | | | | | --o-----o-- GND PWM is duty-cycle modulation. Either simple fixed-clock PWM or some other Sigma/Delta style modulation that has favourable noise properties, like absence of correlation at audio frequencies. R1,C1 product determines 3dB rolloff point. At switch frequencies and linearized around the DC setpoint the circuit behaves as a switched current source driving a capacitor (integrator). The impedance (R1/C1 ratio) needs to be such that the nonlinear I_BE doesn't influence the charge current too much. COMP is comparator input. It can be as simple as a CMOS digital input, relying on the approximate Vcc/2 threshold. It is used to signal full C2 capacitor charge to the PIC to update frequency measurement and allow the PIC to initiate C2 discharge by switching COMP from high Z to ON. Numbers. * To be independent of I_BE, C1 should be as high as possible, meaning R1 should be as low as possible. The collector load of Q1 is a relatively small capacitor so we don't need to worry about limiting continuous current (200mA max for 2N3904 [2]) at least not for the possible fault of a stuck high PWM output. The limit is then set by the maximum drive of the PWM ouput, which is 20mA per pin for a PIC. R1 = V/I = 5V / 20mA = 250 Ohm = +- 220 Ohm. Note that if we discharge at a very high rate with PWM stuck high driving 20mA in the base, the circuit can still go to a max continuous current that far exceeds 200mA. This however seems less likely. The extreme of the fault case is PWM stuck high and COMP (discharge) stuck low or high. So yes, it is still possible to blow up the transistor due to software faults. If this also needs to be avoided, max base current needs to be limited to I_c_max / h_fe_max. * Setting BW to 200Hz this gives: C1 = 1 / 2 pi f R = 3.6uF = +- 4.7uF * The Q1 base current I_BE needs to be compared to the smallest current through R at the highest I_BE. This is the sink current. The source is larger due to larger voltage drop. The sink current is a voltage drop over R1 or I_sink = 0.7V / 220 Ohm = 3mA. The max I_BE is max I_c lowered by the transistor beta. For beta=100 and I_c_max=1mA this is a 300x difference which seems more than adequate. * Filter impedance - Lower bound The currents computed from max R might need to be lowered to keep the operating currents resonable. Lowering will reduce power consumption but increase nonlinearity. 100% sure software safety needs to take into account max I_c when COMP is tied to ground (saturation current: 200mA) and max power dissipation when COMP is tied to Vcc (625mW -> 125mA). - Upper bound There is a clear upper bound to impedance as the C1 charge current needs to be always larger than the max I_BE. Luckily this meshes well with the PWM being asymmetric, as drive current is about 5x larger than sing current at normal operating points. It seems that to keep the currents 1. safe and 2. efficient they need to be quite low, exposing the nonlinearity introduced by I_BE. * C2 discharge time The resistance of a PIC output transistor is about 100 Ohms (estimate grabbed from the web - not in datasheet). We need to make sure that the discharge time of the capacitor through this resistance is far below the smallest oscillator period. Also we'd like to keep the on-time small since it has to be switched explicitly in the PIC. With I_c max 1mA at 20kHz / 50us and a voltage range of 2.5V the capacitance needed is 20nF. This corresponds to an RC time of 2 uS through the PIC output pMOS on resistance. For full discharge we should take say 5x this time which is abut 10uS. The capacitance is bounded by the PIC pin capacitance of 5pF so there is definitely some wiggle room there[1]. With the 100 Ohm estimate, the peak discharge current at 2.5 is 25mA, which is right on the bound. (Maybe that's where max current rating comes from?) The discharge time seems a bit on the high side so we might need a lower capactance/current configuration. Probably 100uA at 20kHz is going to be better. This brings the current down very low thoug: 100nA at 20Hz. I suppose the limit is going to be near the input bias of the buffers used, which si 65pA typical for TL071[2]. * C2 load current range / C2 value Are there any bounds on determining the the order of maginitude of the output current? There is output impedance, which can be quite high but shouldn't be rediculously high so we have trouble buffering it or so that transistor and opamp noise becomes a problem. - Lower current: Energy consumption, nonlinearity due to I_BE, max discharge through PIC output pin pMOS. - Higher current: Noise, buffer input impedance, buffer bias current. The thing to find out is, given we need 4 decades and the resonable largest current range is 1mA -> 100nA, how far can we lower this to bring the current consumption down and allow for less dependence on input RC impedance? I.e. do we want to go much lower than audio and use the oscillator also as LFO, possibly giving up on precision. The analog part probably doesn't have trouble with this, but the digital part might, as it requires larger timers. or even to switch off the feedback loop entirely. It seems straightforward: if the I_BE nonlinearity is an issue, lower the output current. Otherwise pick 1mA. Maybe the nonlinearity isn't an issue at all since it only manifests at thigh frequencies where our ears aren't so sensitive to frequency changes anyway.. Those sounds are mostly used for effects, since they are not so musically interesting. * Controller stability If the non-linearity is an issue, it needs to be dealth with by making the control loop tighter. Does this introduce instabilities? The time constant of the feedback loop is mostly determined by the averaging factor used in the pulse time -> frequency converter in the PIC. Might be best to make the frequency exact, but control the amplitude/ramp speed[4]. [1] entry://20110105-083041 [2] http://www.fairchildsemi.com/ds/2N/2N3904.pdf [3] md5://1997353320958cc168dfb19e7e6a1a6d [4] entry://20110107-122205 [5] md5://e80e5dbb8b58ec9baced943a50902bca Entry: Practical experiment. Date: Thu Jan 6 15:55:46 EST 2011 Nothing yet. Procrastinating... PIC18F2620[1] with 2 digital outputs. I have them wired up on an old board as: RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2 These ports can be used for TRIG inputs. Additionally they can be analog in, measuring cap voltage. Alternatively, RB4-RB7 have interrupt on change, giving one interrupt when one of the 4 changed. These have to be distributed between the oscillator feedback and envelope feedback. From changed requirements[2] the TRIG/DISCH pin needs to serve as an analog input. [1] md5://1997353320958cc168dfb19e7e6a1a6d [2] entry://20110107-122205 Entry: Nonlinear control Date: Thu Jan 6 20:35:57 EST 2011 Taking the circuit output as f, the frequency of the oscillator or filter that is driven by the exponential converter, and the input V, the (average) voltage at the base of the BJT, we have the following model. f = f_0 exp((V - V_O) / V_T), V_T = kT / q * Voltage offset V_O expresses all component mismatches (transistor V_BE offsets, capacitor and resistor errors). This can be calculated once, or at a very low interval (power-on). * Voltage scale V_T is entirely due to operating temperature, needs to be compensated on-line. As mentioned before it would be really interesting to be able to use the feedback control that's necessary to stabilize the oscillator to obtain an _explicit_ estimate of temperature so that this estimate can then be used to drive other transistor in feedforward mode. How would one do this? I suppose using an exact textbook Maximum Likelihood estimator since the model is so simple and the data so plentiful. Entry: Exact frequency sawtooth w. approximate amplitude Date: Fri Jan 7 12:22:05 EST 2011 Instead of going for the "analog" approach of having the oscillator discharge as it crosses a threshold, we could also make the timing exact by generating discharge pulses from the PIC, using the exponential converter just to set the ramp slope. (Juno DCO style). This turns all errors into amplitude errors, which are not nearly as detrimental. It might also significantly relax constraints on the bit depth of the PWM. The voltage point where the discharge happens can then be measured, giving feedback as to how much the ramp slope is mismatched. Note that this doesn't suffer from resolution problems that much, as the measurement is _relative_ to the magnitude of the collector current. This approach would simplify the PIC software and probably allow for some more tricks like hard sync and faking multi-oscillator syncing. Remarks: * How much of the "mojo" is lost this way? If analog sawtooth mojo comes from jitter, i.e. from noise on the trigger level, it is easily faked. Adding a bit of jitter to the digital oscillator timing isn't so much of a problem. Noise could be a triangle distribution from adding two LFSR-generated n-bit numbers. My guess is that the mojo comes from the interaction of discontinuities (i.e. several saws together) and the high frequency sparkle they create when they are not 100% periodic. It would be interesting to figure out if this has been measured before. The mojo myth is well established in the synth community but I've never heard a real explanation execept for the detune. * We can do both analog style triggering and perfect digital tuning and all the effects it allows using the same hardware. * Driving up the current it's possible to use one oscillator as a heater, i.e. when we have say 4 oscs with thermally coupled transtors and we want to operate them at 50 *C, one of them can be used in high-current (high-frequency) setting to control the temperature. [1] entry://20110106-111938 Entry: Other controllers Date: Fri Jan 7 19:54:06 EST 2011 More hands-on verification pending, it seems that the VCO part is solved, and if the temperature control works, digital VCO control and VCA should work too. The remaining question is then how to implement envelopes. These should probably be analog. As opposed to the VCO,VCF,VCA trio which ironically are all current-controlled, the envelopes might work best with voltage controlled resistors, i.e. FETs. The main reason is that exponential attack/decay just sounds really good, especially in the low time constant range. Frankly I don't want to mess with that trying to fake sharp transients digitally. It would probably take significant effort too. So how about the FETs then? I suppose this is an area where the CD4049UBE might shine, as all we need to do is charge / discharge capacitors at a variable rate. The rate resolution is probably not even critical, as long as it is +- logarithmic. [1] http://www.electricdruid.net/index.php?page=projects.envgen7 Entry: RC-decay envelope, FET controlled? Date: Fri Jan 7 20:08:39 EST 2011 RST o---------------------o------o __| | R1 || | PWM o--/\/\/\--o------|| ===== | ||__ | C2 | | | ===== | | | C1 | | | | | o----------o------O Principle: resistance modulation. RST is mostly for resetting and possibly voltage feedback, i.e. ADC or 1/2 time CMOS trigger. In general a FET resistor like this is nonlinear but it is possible to linearize using a simple voltage divider. This sounds nice, but hase some problems: - Very sensitive to V_T for low condictivity (high resistance) - Linear, while we need exponential range. - V_DS needs to be less than the V-V_T distance, which means we can't have a large resistance combined with a large signal. This looks like it's a show stopper. [1] http://graffiti.virgin.net/ljmayes.mal/comp/vcr.htm Entry: BJT current controlled resistor Date: Fri Jan 7 20:12:36 EST 2011 Some early Korg synths and also the recent Monotron[1] (follow links for Monotron schematic) have a Sallen-Key filter with current controlled resistors implemented by BJTs. Might be a good alternative to FETs, which have large V_T spread so might need more calibration. It seems that the problem is that these are all used as AC / small signal resistors, and rely on the large base current to flow. [1] http://www.timstinchcombe.co.uk/synth/korg.html Entry: FET voltage controlled resistor Date: Fri Jan 7 21:07:58 EST 2011 Type: tex The transfer function of a FET in ohmic region $V_{DS} < V_{GS} - V_{T}$ is $$I_D = \frac{2I_{DSS}}{V_T^2}[V_{DS}(V_{GS}-V_T) - 0.5 V_{DS}^2],$$ where $I_{DSS}$ is the drain--source saturation current[1][2]. %[1] http://graffiti.virgin.net/ljmayes.mal/comp/vcr.htm %[2] http://en.wikipedia.org/wiki/Mosfet Entry: Voltage controlled envelope using exp converter Date: Fri Jan 7 22:41:57 EST 2011 Using the exp controlled sawtooth/ramp circuit we could use larger integrator cap values to construct larger slope ramps and feed the ouput to yet another exp converter. If biasing and impedance do not give problems this gives a very simple exponential decay with exponentially controlled time constants. While the "free" exponential decay that comes from an RC network seems much simpler, a voltage or current controlled resistor that works at DC isn't exactly cheap to build[1]. This circuit could also serve as an exponential pulse oscillator which decays into a saw by varying the amplitude. (??) --o-----------------o-- Vcc | | | > ===== C2 > R3 | R2 > TRIG/ o------------------o---/\/\/\/\--o | DISCH | | o--o Vout R1 / | | PWM o---/\/\/\/--o---|/ Q1 | | / | |\ o-|/ Q2 | V |\ C1 ===== | V | | | | | | --o-----o-----------------o-- GND Instead of R3, the output could also be a current into an opamp virtual ground biased around 1/2 Vcc. As far as careful design goes, this circuit is horrible. But can it be made to work with proper driving and some voltage feedback from Vout? Safety R2 is necessary for limiting Q2 base current when DISCH is set to Vcc, driving Q2 into deep saturation. Range The useful range over C2 is quite small. For a 100x envelope range it's about 100mV. The main problem however is to initialize the C2 voltage to the proper bias before starting the linear charge ramp. In order to solve the biasing problem of Q2, the following re-arrangement will probably be better. --o--------------o-- Vcc | | | > ===== C2 > R3 R2 | > TRIG/ o---/\/\/\/--------o------o | DISCH | | o--o Vout R1 / | | PWM o---/\/\/\/--o---|/ Q1 | / | |\ o-----|/ Q2 | V |\ C1 ===== | V | | | | | | --o-----o--------------o-- GND Here the voltage at C2 and base of Q2 can't go over V_BE. The envelope swing will be maximum, only limited by the saturation voltage of Q2. Releasing the DISCH will start the ramp over C2 which will first take Q2 out of saturation (a small envelope delay) and then will start decreasing the current through R3 creating an exponential curve. When Q1 reaches saturation due to C2 charging, the voltage over Q2 base will be small enough to make the current through R3 negligible. I.e. it's past the useful part of the curve. The only thing to be careful about is the base current of Q2. Once DISCH is off, it will be provided by C2, leading to a faster discharge of C2 in the beginning of the ramp. However, R3 can be relatively large, which makes the bias current small. There seems to be a problem with size of C2 though: it needs to be large to provide Q2 bias current, and R2 needs to be relatively large to limit Q2 saturation current, so the product is large, which makes discharging C2 a time consuming operation. Is the following reasoning correct? R2 needs to be relatively small to keep the R2C2 time constant small because C2 will be relatively large. This means Q2 will be deeply saturated. This allows for some wiggle room to make the circuit not depend too much on h_fe of Q2. This saturation current will be high compared to the current through Q1, which will make C2 drop voltage fast. However, in order for this initial relaxation not to show in Vout, the base current of Q2 needs to become small in relation to the current through Q1 _before_ Q2 leaves saturation. Then the ramping voltage will bring Q2 out of saturation, starting the exponential decay with a slight delay. This delay needs to be small compared to the rise time of Vout. That might be a problem. Conclusion: Q2 biasing seems to be too sensitive to component parameters, so it might be best to use feedback for setting the bias point. Something like this: --o-----------------o-- Vcc | | | > ===== C2 > R3 | > R2 | | | o----o--o V_out DISCH | | | TRIG/ o---/\/\/\/--------o------o > | | | > R4 | R1 / | > | PWM o---/\/\/\/--o---|/ Q1 | | / | |\ o-----o--|/ Q2 | V |\ C1 ===== | V | | | | | | --o-----o-----------------o-- GND With DISCH and Q1 current source disconnected, the transistor will be in forward active mode, and the V_out bias point will depend on the current gain b as (1 + b/b_0) where b_0 is the nominal current gain. V_out nominal could be set to 1/2 Vcc, allowing for about 50% current gain mismatch. It seems that it really isn't straightforward. [1] http://www.avtechpulse.com/papers/vres/ Entry: No analog synths without OTAs! Date: Sat Jan 8 18:15:47 EST 2011 Too bad they're a dying race. I just received the LM13700 dual OTA from Futurlec at $1.50 a piece. That's not bad, but if you compare it to TL074 quad opamp at $0.27 there does seem to be some scarcity at play. Similar price on eBay. To compare, not an OTA, but the SSM2164 VCA is $10 on eBay. Since the hacked ramp -> exp envelope generator doesn't seem to be a good idea, it seems the only real option is to implement the circuit as a cutoff-parameterized linear filter responding to a step function. Entry: Random non-tested circuit: Ladder integrator Date: Sat Jan 8 18:52:18 EST 2011 Something I was thinking about in another post but doesn't do what I need. This is an integrator -- needs an output buffer. Might not be so useful. I guess the capacitor could just as well go on the output instead of between the two current mirror legs. o---------------o Vcc | | \ / Q3 >| |< Q4 |--o--------| / \ / | \ o----o | | | -- | \/ D1 | -- C1 | | || | o-------||------o--o V_out | || | | | V1 (+) / \ V2 (-) o--|/ Q1 Q2 \|--o |\ /| V V | | o-------o-------o | | I0 \ \|---o Exp controller /| V | --o-- GND This is a differential pair Q1,Q2 with a current mirror load Q3,Q4. The diode D1 is for some extra DC bias fixing one end of the capacitor C1 (might not be necessary). The Q1,Q2 collector curents have a ratio I1/I2 = exp(V1-V2 / V_T) while their sum I1+I2 = I0 is set by the long tail current source. The difference I1-I2 flows through the capacitor. Entry: Envelope: One pole variable filter using OTA. Date: Sun Jan 9 09:51:38 EST 2011 Implement envelope generator using a full DC one-pole variable filter. ( Note that an envelope generator only needs a 1-quadrant multiplier since both control voltage and output voltage do not cross zero, so there might be a simpler way. However, the 1-quadrant multiplier, i.e. current-source biased commion emitter configuration has biasing issues which are solved by the differential pair. This then gives 2-quadrant operation for free. Looks like the OTA (without current-mirrir output) really is the simplest solution. ) A 1-pole lowpass OTA filter is a variation on the OTA integrator which has current output into a capacitor. The lowpass has additional voltage feedback from the output to inverting input which makes current into the capacitor depend on the voltage difference between input and output, creating the typical low-pass response. In the schematic this looks as if the (-) input transistor is replaced by a diode. Imperfections: * If this is implemented with a non-linearized OTA, how important is the nonlinearity? Quite. For the envelope follower it limits the slew rate significantly. Seems the question is about how much of the wave shape will be effected by this. A little bit of squashing on an exponential decaying curve isn't going to hurt much I think. Maybe this can even be used as an effect? To give more "punch" by driving a larger gate signal. * Offset: since we need true DC performance, offset needs to be compensated. Otherwise the envelope won't go to zero, or will cross it. The offset voltage needs to be taken care of. This is one property that makes the direct ramp->exp generater look interesting again. Entry: Envelopes: problem is offset Date: Sun Jan 9 09:55:45 EST 2011 So, sticking to the full DC 1-pole LP, the problem is offset voltage. Can this somehow be incorporated into the design, knowing that envelopes will always add to another control signal. Since the base control level will always come from a PWM signal, all compensation can be moved to there. Problem is the lin/log thing though: offset is more of a linear, constant compensation, instead of a log one. I.e. for very small control voltages the offset's relative component would be large, killing the relative error property. One thing that does work for the circuit is that the current goes to zero perfectly. What about using a current mirror on the cap output? Problem with that is the current is not unipolar, and the current is highpass (integral of 1st order lowpass). So, how good does the offset need to be? - VCA: it should be possible to turn an oscillator off. - VCF: not so critical as there is usually some programmed offset anyway: env is only used on top of base line filter setting. Entry: Differential amplifier offset Date: Sun Jan 9 11:00:25 EST 2011 Offset becomes important whenever full DC frequency range is required, i.e. implementing a low-pass filter. This seems to manifest itself as the zero-in-zero-out requirement over a large dynamic range. How does one usually deal with this? Entry: RF envelope generator Date: Sun Jan 9 11:04:16 EST 2011 So, (following part of Gert's reasoning) what about using the amplitude of a very high frequency sinusoid as the output of a circuit? I.e. if DC is a problem, let's modulate it up. A decaying exponential can also be generated using a 2-pole circuit followed by a peak-detecting demodulator. The problem with this is that for very long decay times, the poles become very sharp, which leads to unstability due to noise and non-linearities. Entry: Env mod: add or multiply Date: Sun Jan 9 11:15:41 EST 2011 Mixing log and linear control voltages it becomes hard to keep track of which signals need multiplication, and which need addition. I.e. filter envelope depth: do we add pre-exp or post-exp? Pre-exp seems best from numerical pov, but this doesn't seem to correspond to how i.e. the Juno 60 works: envelope doesn't bring filter to 0. Entry: Moog VCF: current input differential stage. Date: Sun Jan 9 11:53:52 EST 2011 As analysed by Antti Huovilainen[1][2]. Is this just a differential current input voltage buffer? I.e. provide a fixed voltage reference on emitter for current input, but provide a variable voltage on collector. [1] http://www.mitpressjournals.org/doi/abs/10.1162/comj.2006.30.2.19 [2] md5://81ef26b98b858bfc7ea351850b7f8872 Entry: Modular system Date: Sun Jan 9 12:05:49 EST 2011 To gear up for production of prototypes it might be a good idea to think about some way of modularizing the system. Some principles: * Central symmetric (analog) power supply. This should be a "clean" supply (i.e. linearly regulated) such that V+ and V- can be used as signal references without risk of power supply bleed. * Separate digital and analog power supplies. I'm not sure if this is really necessary, but most mixed A/D design do seem to go by this principle. The reason is that digital supplies are necessarily dirty due to CMOS charge/discharge spikes, while linear circuitry is more smooth, possibly depending on signal but mostly fixed bias currents. * No panel potentiometers on the separate modules. We're going for a fully digitally controlled analog synthesizer. Pots are expensive, bulky and the nonlinear ones are usually not very well tapered. Building a controller can be a separate project (i.e. using pots instead of rotary encoders, since they still give much more resolution). I would like the basic synth box to fit in a suitcase. * No trimpots. Not really an interface issue, but reflects basic design: no mechanical calibration. All calibration needs to be designed in and computer controllable, either once at fabrication, possibly using external circuitry, or on-line using feedback control. * Final design: no patch cables. All routing should be digitally controlled analog switches/muxes. External outputs are optional. * Virtual ground inputs referenced to analog mid voltage, direct opamp outputs. Current configured as 100k = unit voltage gain. This gives several advantages: - Free input summing and cheap input scaling (resistor). - Direct connection of NPN (negative) or PNP (positive) transistors as exponential converters. - Free fanout. We might use the convention that negative currents correspond to positive signals, as this allows for more common and cheaper NPN transistors to be used for current gain setting. Then negative voltages should probably also correspond to positive control signals to keep the simple resistor-summing rule. Note that signal routing needs to be solved centrally, as each module has a variable number of inputs and outputs. For now it could be just el cheapo bell wire patch cables from female SIP headers. * Shared digital bus for low-speed data comm (setpoints and calibration data). Probably I2C. * Clock. It might be a good idea to have a shared high speed clock for synchronous microcontroller operation. * Physically, the shared bus could be used to support stacks, and to allow for later expansion, i.e. simply by widening the connectors. Board dimension could be one of the easy to find perfboard sizes. This gives the following duplicated bus lines for each card: analog: +,0,- digital: +,0 i2c: SCA,SDL clock: CLK Then each card has a number of opamp (voltage) outputs and virtual ground (current) inputs. Entry: Stacking headers Date: Sun Jan 9 13:51:08 EST 2011 Where to buy? [1] has 5x 8p for $2.50. [2] has 2x 8p + 2x 6p for $1.50 Samtec has them[5] but apparently expensive. They can be bought in bulk at uconnector[4] for about $0.05 per connector, which is close to Futurlec prices. I'm thinking that overall the hassle to source these might not be worth it.. There has to be a simpler solution. [1] http://shop.moderndevice.com/products/8-pin-stacking-headers [2] http://www.adafruit.com/index.php?main_page=product_info&products_id=85 [3] http://www.iheartrobotics.com/2009/04/arduino-stacking-headers.html [4] http://www.4uconnector.com/online/itemagrid.asp?seriesdesp=2.54+FEMALE+HEADER+PLUS+TWO+BASE+DIP+STRAIGHT+HEIGHT%3D13.59MM&seriesno=0197&GroupNo=01&groupdesp=Pin+%2F+Female+Header&itemnum=5324&sample=&seriesnum=96& [5] http://www.iheartrobotics.com/2009/04/arduino-stacking-headers.html Entry: Evelopes again Date: Mon Jan 10 17:57:34 EST 2011 1. Decay needs to be exponential 2. Attack, well... The low-pass exponential is a hack anyway as there is no real physical relation. Attack is either instantaneous, or it is "blown" or "bowed", i.e. a consequence of human actuation. So what about sticking to the exponential converter anyway, design for accurate large range decay time, and find a hack to make attack longer than instantaneous. Maybe here switched resistors could work. Entry: Analog control voltages Date: Mon Jan 10 18:31:21 EST 2011 Something Gert mentioned made me think. What about analog control signals? In the current design, the calibration is part of a complete control loop spanning digital PWM to (digitally measured) frequency output, with analog circuitry in the middle. In this scheme there is no way for for analog controls voltages/currents to benifit from the digital compensation/calibration. Could we get to something like 1V/octave in a predictable way? Or say a less wasteful 250mV to keep things within the 5V supply. Currently the compensation is about: - Temp comp, which is voltage SCALE - Component mismatch, which is voltage OFFSET The base line seems to be that OFFSET compensation is easy to share with analog modulation: Digitally set base offset + add analog signals before they go into the transistor. The SCALE compensation is another story. Bringing voltage scale compensation into the analog domain will require some extra components. ( More multipliers, or some high frequency choppers. ) The question is then: is it worth it? Or should analog control signals simply be digitized and run through the digital compensation? Or, in the case of control knobs for instance, do we really care that much about a little bit of scale offset? Meaning, can analog control inputs go uncompensated? Conclusion: it's not worth it. Leave room for hacks (i.e. current inputs) but design for minimal components when all controls are digitally compensated. Entry: 2-Scroll modified SVF Date: Wed Jan 12 12:13:58 EST 2011 This needs a bit more thought. I tried but can't build it just out of the blue.. I need a symbolic model that can be verified, i.e. some Haskell code? Entry: Prophet 5: A/D and D/A resolution Date: Wed Jan 12 18:34:26 EST 2011 I found the Prophet 5 service manual[1], as it is a nice example of a digitally controlled analog instrument. Made me think: maybe high a/d resolution isn't so necessary for storing patches: approximate settings are just fine. It's when D->A is used for continuous control that problems arise. The prophet uses 7 bits for most CVs. and 14 for the frequency CVs to allow for fine tuning. Tuning happens in octaves. The Prophet uses a single 16 DAC for both D/A (synth control) and A/D (potentiometer readout), combined with CD4051 ($30 Tayda, $50 Futurlec) analog muxes and sample-and-hold circuitry. [1] http://www.hylander.com/moogschematics.html Entry: PWM vs. DAC+MUX Date: Wed Jan 12 21:12:51 EST 2011 Obviously, DAC+MUX+SH take up board space and cost something, but wouldn't it be a lot simpler to just use that tried-and-true approach instead of using PWM? Exactly what is gained? The main difference wrt. old chips is CPU speed. Entry: Synth: just build it? Date: Wed Jan 12 22:07:01 EST 2011 Detach from the possible, attach to the feasible. I think all of the obvious mistakes are removed. I don't know what to do with the envelopes yet, but maybe that's really something to worry about when I have something running. The VCO, VCF, VCA should be enough to start with. For the envelopes, one thing to figure out is what the max rise and fall times are in the current PWM setting. Maybe there is no problem at all, and maybe using 2 regimes could solve it, using 2 charge/discharge resistors, one for envelopes and one for sustained sounds. Entry: Approximate PWM Date: Wed Jan 12 22:20:48 EST 2011 Anything well above audio frequencies does not need to worry about what the noise ripple looks like, so some form of approximate PWM/SD might work. The basic idea is that handling say 10 PWM signals in software is not going to pan out. It might be better to use approximate PWM/SD and compensate for the slack in missing deadlines. Maybe it's even possible to use one PIC as a dedicated modulator, running without interrupts, and solving the control problem in another chip. Entry: SVF, freq through feedback? Date: Thu Jan 13 12:08:46 EST 2011 How well does it work to set the frequency using the output feedback only? Not so well it seems, as this requires fairly large dynamic range on the pot: frequency is proportional to square root of ratio. Overall: SVF is not so useful as a manually controlled circuit due to the reliance on the dual antilog pot for frequency and the antilog for resonance. Building a guitar pedal with 2 SVFs might be an interesting project though, especially in combination with overdrive. Entry: Analog synths on the market Date: Thu Jan 13 16:24:10 EST 2011 For monophonic synths, it seems that there are currently quite a few reasonably priced options available. I'm most surprised about the monotron. It could be so much more with a bit of controls added... Dave Smith Instruments Mopho[1]. $325 (1 voice) Tetra[4]. $800 (4 voice) Prophet 8[6]. $1550 (8 voice) Evolver[7]. $550 Doepfer Dark Energy [2]. $625 Korg Monotron [3]. $50 MFB-SYNTH LITE II $327 The Dark Energy supposedly[2] uses the curtis VCF (CEM3320) which I thought was no longer manufactured. They must have some own stock then. The warbly, distorted resonance is from that chip then? The Mopho has some internal feedback mechanism. I wonder what that's about. EDIT: main out -> filter in if the input jack is not connected. [1] http://www.youtube.com/watch?v=fRjxmcrzWbA&feature=related [2] http://www.youtube.com/watch?v=QLs6XQxO6uE&feature=related [3] http://www.youtube.com/watch?v=jj0zjBvRf0E [4] http://www.youtube.com/watch?v=NvxRrA991ZE&feature=related [5] http://www.youtube.com/watch?v=jrqTUnY9lCM&NR=1&feature=fvwp [6] http://www.youtube.com/watch?v=HquWX0izM9I [7] http://www.youtube.com/watch?v=uXn-DiROW04 [8] http://vermona.com/index.php/en_home.html Entry: Synth requirements revisited Date: Thu Jan 13 16:33:57 EST 2011 Stable basics. These are mostly about complexity and price. - No manual calibration (trimpots, hand matching components) - No obsolete or near-obsolete components - Digital tuning, either direct or using feedback control - Minimal discrete component count Some early assumptions overturned: - Not allowing analog CV modulation is a bad idea. While it might be a nice way to get to an incrementally working design, you really want to leave open audio-rate modulation of the filter and oscillator frequencies. It's virtually for free on the analog side, once you have the exp converter working. Problem is calibration though: feedback calib is probably simple, but analog calib costs something. - On-line control might not be so essential for anything else than the oscillators. If it's good enough for the prophet 5 and the mopho, 7 bits should be plenty for my little project too. Of course, using the filter as an oscillator does up its requirements. EDIT: mopho filter cutoff does respond to more than 7 bits, and I believe so does the Prophet knob control. Entry: Analog calibration Date: Thu Jan 13 19:17:15 EST 2011 It seems clear that going for full digital calibration gives up on some nice modulation abilities, unless external control signals are routed through an equally compensated gain/offset circuit. What is the cost offset here? One of the following - Analog one-time calibration (trimpots / component matching) - Digital trimpots - Analog multipliers for external controls It seems expensive. Looks like it's an either/or: stick with classical manual calibration, or do it digitally but loose analog CV precision. So I reached the same conclusion as [1]. That's two votes for simplicity and grit. [1] entry://20110110-183121 Entry: Non-oscillator feedback Date: Thu Jan 13 19:17:49 EST 2011 ( For reference. I'm rambling, I don't think this is an issue. ) Problem I have with other antilog control currents compared to oscillators is that there is no direct way to measure the circuit output. I had this idea of adding an oscillator cap to each controller, so it can be switched between osc and its normal function. I.e. driving a differential pair, the diff pair's inputs could be pulled to zero, reverse biasing the BJTs and so isolating the differential pair. However, this might not be necessary. There is probably plenty of opportunity to measure the output of the circuit. Envelopes times can be measured just fine as long as you measure at say 1/2 amplitude. Filter should be fine too if put into self-osc mode, and with full digital control that's always possible. However, the output would be less predictable though. Entry: The Korg MS20 filter and reverse saturation transistors Date: Fri Jan 14 10:43:25 EST 2011 In the paper[2] that can be found at Tim Stinchcombe's Korg[1] page it is explained how variable resistors are implemented using BJTs in reverse saturation mode. What I don't fully understand is why it is reverse. From what I can find in the derivation it has something to do with the reverse current gain being much lower than the forward gain. As a result, it is only the forward biased Base-Collector diode that significantly contributes to the resistance, which is the deriviative of the V->I curve over the Emittor-Collector terminals. Picking a random 2N3904 PNP and measuring with a multimeter I find for forward and reverse gain: 288 and 9. [1] http://www.timstinchcombe.co.uk/synth/korg.html [2] http://www.timstinchcombe.co.uk/synth/MS20_study.pdf Entry: Home made PCBs Date: Fri Jan 14 21:59:55 EST 2011 I've been looking around for options to home-make some PCBs. Building perfboard circuits is too labour-intensive, and prototyping services are too expensive if a reasonable lead time is expected. BatchPCB[1] is 3 weeks, though they seem to be a nice inbetween in case production is considered, i.e. through Gold Phoenix[2]. However, for my current needs I want fast turn-around with not too much effort. I recently ran into a page about DIY PCB etching using laser printer toner as a resist (etch stop)[3]. Glossy photo paper is used to print the (mirrored), and a hot iron is used to transfer the plastic based toner to the iron clad PCB. Here's another one that recycles magazines instead[4]. Also possible with inkjet and pigment ink[7]. Some commercial paper solution[9]. Another hint: use very thin PCB, so they can be cut with a paper cutter. This[5] is an interesting thread about other ways, like using a cricut cutter and aluminum foil. Homemade conductive ink[6]. Commercial conductive ink[8]. Conductive copper tape [10]. [1] http://batchpcb.com [2] http://www.goldphoenixpcb.biz [3] http://fullnet.com/~tomg/gooteepc.htm [4] http://www.riccibitti.com/pcb/pcb.htm [5] http://forums.xkcd.com/viewtopic.php?f=36&t=56389 [6] http://www.ehow.com/how_7657235_homemade-conductive-ink.html [7] http://techref.massmind.org/techref/pcb/etch/directinkjetresist.htm [8] http://www.radioshack.com/product/index.jsp?productId=3964901 [9] http://www.techniks.com/ [10] http://www.amazon.com/s/?ie=UTF8&keywords=conductive+copper+tape&tag=googhydr-20&index=aps&hvadid=4038447375&ref=pd_sl_5ae0q56oo_e Entry: OTA SVF Date: Sun Jan 16 22:01:07 EST 2011 Instead of the traditional gain-settable integrator, use a fixed gain double (leaky) integrator, and 2 variable feedback. 1 for cutoff frequency and 1 for Q. Would this work? I'm thinking: what about driving the input diode of the LM13700 directly using the filtered PWM? As long as we limit the current this should work just fine. EDIT: nope, it's not a diode. Entry: Charge controlled LED Date: Mon Jan 17 00:04:09 EST 2011 As the saying goes: stay away from inductors. I've been looking into efficiently driving LEDs without series resistors but it seems that series resistance for inductors used in boost/buck is not really negligible. The thing with LEDs is that they can be pulsed. As long as you stay below the rated current on average things should be fine. Is it ok to put a large voltage over them for a short time? That way they can be fed from a capacitor and effectively charge controlled. [1] http://www.piclist.com/techref/io/led/pulse.htm Entry: Chopper techniques (Envelope?) Date: Mon Jan 17 11:23:17 EST 2011 Coming back to the Envelope generator problem. I one of the approaches I proposed, it is necessary to compensate for low offset voltage. The main idea is that you want a VCA controlling current to decay to zero very accurately instead of an offset voltage. EDIT (Wed Sep 28 15:14:15 EDT 2011): The main idea behind going through the trouble of making analog synth circuits is to get the those cool sounding nonlinearities for free, without any digital, unnatural sounding aliasing artifacts. A chopper is a sampled system, so might alias. However, when it's used in a linear part of the circuit it shouldn't matter. [1] http://en.wikipedia.org/wiki/Chopper_%28electronics%29 Entry: Prophet 8 Date: Mon Jan 17 19:39:01 EST 2011 Review[1]. Some remarkable features: - Step sequencers - Modulation matrix. - Oscillator "slop" mopho[2] [1] http://www.youtube.com/watch?v=6oS6J2sToZM [2] http://www.youtube.com/watch?v=HD_RyYb7ndM Entry: CEM3320 Date: Tue Jan 18 22:23:01 EST 2011 The CEM3320 datasheet[3] says the variable gain amplifiers are current in, current out and the gain is set by a voltage. I_OUT = (I_REF - I_IN) A_IO e^{-V_C / V_T} I_REF flows through a feedback resistor from buffer output to input. What would that circuit be? Maybe a variant of the Basic Transconductance Multiplier circuit leading to the a Gilbert cell in [4] -- something using the translinear principle[5]. [1] http://curtiselectromusic.com/Product_Overview.html [2] http://www.electricdruid.net/index.php?page=info.cem3320 [3] http://curtiselectromusic.com/uploads/CEM_3320_Long.pdf [4] http://www.analog.com/static/imported-files/tutorials/MT-079.pdf [5] http://en.wikipedia.org/wiki/Translinear_circuit Entry: Next Date: Sun Feb 6 09:54:29 EST 2011 Need to get going again after lack of time due to contract job overhead. The main goal is to get over the prototyping fear, build board with: - PIC18F2620 to 5V TTYUSB cable. - 3 exp converters connected to: * One saw tooth oscillator * One OTA-based VCA * One 2-pole OTA-based SVF The purpose is to test feasibility of the exp converter design and to get the basic software infrastructure up. Entry: Relaxation oscillator Date: Sun Sep 30 09:07:30 EDT 2012 Current source into capacitor + threshold-based reset (cap discharge). Should the discharge be a discrete component (PIC only controls charging current) or should discharge be done in ISR? ISR is more efficient with component count. Big question: how large is the noise going to be? Problem is that the voltage range of interest is say 0.5 - 0.7 V, which is tiny. A lot of resolution is lost here. 5V -> 0.2 is a factor 25. In theory, making the filter cap large enough, resolution is not the problem, but in that case the control time constant might be a problem. I'm starting to thing this whole idea is not very realistic. What about prefixing an opamp? Pff... this looks a bit like a dead end. I'm loosing interest. Entry: Platforms Date: Thu Oct 4 15:17:29 EDT 2012 1. PIC18 + Staapl for the Kmook Grunt synths. 2. Something with C and Haskell. Entry: Follow the Joy Date: Fri Oct 5 14:35:56 EDT 2012 Time to make noise! Next step: MIDI. Probably best split into 2 parts: a USB->something hub and a something->sound collection of chips. The something should probably just be standard 38kHz serial MIDI, with debugger in ICD ports. Since I have plenty of MIDI outputs, let's just use that for now. Can even do in non-standard (no opto coupler receiver). Since I have this string tendency to go depth-first, it might be good to create a collection of non-essential elements. Essential - Midi parser on sheepsint/grunt. Non-essential: - USB -> Serial/MIDI converter PIC18F2550/4550 - Isolated MIDI input circuits (optocouplers). - Output isolation: power supply filtering, i.e. inverters? Entry: MIDI Date: Mon Oct 8 20:04:39 EDT 2012 Midi physical connection[1][2]. 1-Way current loop driven from 5V (current source) to the output of an inverter (current sink) connected through a couple of 220k resistors limit the current. The opto-coupler LED is included in this loop. While the voltage on current source is the UART voltage if the current loop is open, when closed it will produce a current that is the inverse of the UART signal, which will again be inverted by the optocoupler's output transistor/resistor network, to be fed into the receiving UART. I cut a HOSA 3ft MIDI cable in half and find 4 wires + shield: (1) NC b lack (2) GND cable shield (3) NC yellow (4) CSINK white (5) CSRC red Looking at the MIDI output of the BCR-2000 in S-1 mode shows indeed a 5V serial signal on CSRC/red that would go straight into the serial in. To make a non-isolated MIDI work, connect the shield from the midi cable to ground of the receiver circuit, and power the receiver with batteries. [1] http://www.midi.org/techspecs/electrispec.php [2] http://pinouts.ru/Home/MidiOut_pinout.shtml Entry: 1220 broken Date: Mon Oct 8 21:25:38 EDT 2012 PK2 works with the 18F2550 but not the 18F1220. Strange. Maybe try the 1320? Nope... so I can either continue with the 2550 or waste time on getting the other chips to run. Probably best to stick to 2550. Entry: 18F2550 serial input Date: Mon Oct 8 21:30:28 EDT 2012 Next: serial input at midi rates. Entry: Alsa MIDI using BCR2000 Date: Tue Oct 9 10:01:32 EDT 2012 The /dev/midi doesn't seem to work properly, but alsa does report the correct number of ports when switching between USB modes on the controller: # U-1 tom@zoo:~$ cat /proc/asound/BCR2000/midi0 BCR2000 Output 0 Tx bytes : 0 Input 0 Rx bytes : 0 tom@zoo:~$ cat /proc/asound/BCR2000/midi0 BCR2000 # U-3 Output 0 Tx bytes : 0 Output 1 Tx bytes : 0 Output 2 Tx bytes : 0 Input 0 Rx bytes : 0 Input 1 Rx bytes : 0 So, how does alsa MIDI work? See [2]. tom@zoo:~$ aconnect -i client 0: 'System' [type=kernel] 0 'Timer ' 1 'Announce ' client 14: 'Midi Through' [type=kernel] 0 'Midi Through Port-0' client 24: 'M Audio Delta 1010' [type=kernel] 0 'M Audio Delta 1010 MIDI' client 28: 'BCR2000' [type=kernel] 0 'BCR2000 MIDI 1 ' 1 'BCR2000 MIDI 2 ' client 128: 'Virtual Keyboard' [type=user] 0 'Virtual Keyboard' tom@zoo:~$ aconnect -o client 14: 'Midi Through' [type=kernel] 0 'Midi Through Port-0' client 24: 'M Audio Delta 1010' [type=kernel] 0 'M Audio Delta 1010 MIDI' client 28: 'BCR2000' [type=kernel] 0 'BCR2000 MIDI 1 ' 1 'BCR2000 MIDI 2 ' 2 'BCR2000 MIDI 3 ' tom@zoo:~$ Connect the virtual keybaord to the port B on BCR2000 in U-3 mode: aconnect 128:0 28:2 [1] http://alsa.opensrc.org/AlsaMidi [2] http://alsa.opensrc.org/AlsaMidiOverview Entry: Cleaning up digital out Date: Sun Nov 4 00:06:45 EDT 2012 This needs an inverter that's run from a clean power supply. Additionally, running this at about 1.0-1.2V would give a good V-range for an exp converter, as it has midrange around 0.5-0.6V which could drive a bipolar base directly. - a clean voltage supply - inverter running of of 1V maybe just 2 diodes (transisto diodes?) connected to V+ through a current-limiting resistor. this would set the "mid level" current. maybe there's a way to set the 0 an 1 levels this way also? have 2 diodes, one with minimal current, one with maximal current, then gate this to transistor bases. to keep the currents low, 2 diodes could be used on the high end. it seems a differential pair is a better fit for this. this then has a 0V level and a diode-controlled 1 level. what about the uC shorting a diode stack? difference between 1 and 2 diodes? Entry: Production Date: Sun Nov 4 00:52:58 EDT 2012 I need to aim for production, especially if designing for a particular fab. I thing I saw a fab where SMT transistors and resistors where "free". Looking at that those behringer effects pedals it seems that these days analog electronics do not have to be expensive.. Entry: Test setup Date: Sun Nov 4 01:34:05 EDT 2012 nekobee.so through jack-dssi-host connected to UMA25S. Entry: always_inline Date: Sun Nov 4 14:56:12 EST 2012 I wonder if it is possible to just write the whole thing in C, carefully using inline functions and SA variables. See aksi always_inline[1][2]. [1] http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Function-Attributes.html [2] http://stackoverflow.com/questions/8381293/how-do-i-force-gcc-to-inline-a-function Entry: UMA25S Date: Sun Nov 4 15:58:46 EST 2012 Trying out the Behringer U-CONTROL UMA25S USB MIDI Controller I picked up for around $50 on ebay. Overall OK, but the velocity curve sucks. It's probably best turned off. Keys have about the same feel as the AKAI I got earlier. I wonder if I can find some unweighted synth controller.. EDIT: I opened it up, and basically this is just a plastic key pressing down on 2 buttons using a rubber cushon, one pushbutton mounted a little lower than the other. I suppose the time diff then gives velocity. I wonder what gives my old JV-80 keyboard that different feel. Entry: Scanned synthesis Date: Sat Nov 10 20:34:23 EST 2012 Been playing with my scanned synthesis patches, and the main thing that starts to bug me is the metallic sound. There is no movement in the sound at all, which makes it sound unnatural. What to do about that? Add some phase rotation? Some weblinks: "... and many of the more abstract sounds would be lost without a heavy dose of chorus[1]" wich is the same conclusion as above. [1] http://www.kvraudio.com/product/scanned_synth_pro_by_humanoid_sound_systems [2] http://www.soundonsound.com/sos/oct07/articles/scannedsynthpro.htm Entry: General Music (GEM) S2 Date: Wed Nov 14 20:05:43 EST 2012 The General Music (GEM) S2[1]. Manual I found at [3], linked from [2]. [1] http://www.sonicstate.com/synth/gm_s2/ [2] http://www.yamahaforums.co.uk/forum/viewtopic.php?f=20&t=41 [3] https://dl.dropbox.com/u/8252519/GEM_S_Manual.pdf Entry: UMA25S + GEM S2 Date: Wed Nov 14 19:04:23 EST 2012 Connected the UMA25S to the GEM S2 a and it doesn't seem to have this velocity problem. The problem probably is with the softsynth I used to test it. So I wonder, what is the real (physical) relation between velocity and amplitude that makes a commercial keyboard synth sound "normal"? Entry: Exp converter Date: Sun Dec 16 21:13:31 EST 2012 R/DD + R/C -> base voltage R/DD network is a simple way to convert 3.3V to a range that makes sense for base voltage: 0 - v_mid - 2x v_mid. Transistor behaves as diode for this network, and 2 diodes in series behave as one diode with different parameters. Entry: i3 Detroit Public : Analogue Synth Brainstorming Date: Wed May 29 19:14:03 EDT 2013 [1] https://groups.google.com/forum/?fromgroups#!topic/i3detroit-public/DdowdbqGvGc [2] http://i3detroit.com/wi/index.php?title=Modular_Analog_Synthesizer Entry: M-audio fasttrack pro Date: Thu Aug 8 19:11:37 EDT 2013 - Functions as a stand-alone 24-bit/44.1kHz A/D converter Entry: exponential IDAC (EIDAC) Date: Sat May 10 18:50:40 EDT 2014 Using MCP4922 it's possible to make an sinking EIDAC by using 3 thermally coupled transistors with matched V_BE -> I, and using one of them in diode configuration connected to the V_REF, then using buffered output. In buffered mode, V_REF needs to be 0.04V away from both rails. It might not even be necessary to match the transistors, as mismatch shows up as a voltage difference. With 12 bit we have 4096 taps say with 0.6V max this is (/ 0.6 4096) 0.15mV So let's just make sure they are thermally coupled. I have the MCP4922 available here. Looking around, I also find the DAC8420, which has 4 outputs and LO/HI reference inputs. This might be useful as this can also set the current range corresponding to DAC=0. Nice feature, but it's a $44 part! Actually, the feature is necessary if temperature compensation is desired. And it is; over a 30 degrees range the difference in $V_T$ is about 10%. I wonder if it's possible to just lift the DAC's ground up by the low voltage bias. Sure is cheaper than finding a dual reference DAC. What is the effect on the digital inputs? Absolute maximum is VSS–0.3V - we're going to be over that. Measured 2N3906 NPN 1mA -> 0.63V 1uA -> 0.44V 0.21V per 3 decades. Going down to 0.3V means another 1.5 decades to 30nA. I guess that's possible, but would require quite a large resistor: 4.7V / 30nA -> 156M I'm guessing it's going to be OK to go over it a little during data transfer. There is probably a diode to ground so let's connect the inputs with a resistor to catch the drop. What about this: - connect through diode with 10k pullupp - run SPI clock / data inverted Seems to work, except that a 1k resistor was needed from opamp output to ground. LM324 can't sink much current? Maybe add a transistor to bridge the voltage. [1] entry://../math/20140510-190720 Entry: Dual REF DAC Date: Sun May 11 10:24:31 EDT 2014 MAX5105 / MAX5106 might be good too: cheaper 2ref, but 8 bit only http://www.maximintegrated.com/datasheet/index.mvp/id/2476 I think I'll stick to the lifted DAC approach. Entry: EIDAC calibration Date: Sun May 11 10:46:49 EDT 2014 Quite a mile stone that EIDAC. Circuit needs some polish. Mostly error analysis and compensation. I worry about the input offset current for the uA set point as it gets within 5% of the offset current. It would be good to find out if the bias can be done differently, i.e. the range set to one decade/octave and then just scaled with an opamp? Tempco stuff can maybe be done by putting all transistors on a single package like MMPQ2222A[1]. So what about offset? Transistor mismatch results in a constant V_BE offset. Is that still temperature dependent? [1] http://www.digikey.com/product-detail/en/MMPQ2222A/MMPQ2222ACT-ND/458989 Entry: Oscillator Date: Sun May 11 10:47:41 EDT 2014 The simplest way to calibrate seems still to use frequency output of an oscillator driven with the set current. This is a measurement that can be done very precisely on a uC. So how to get it to oscillate? Seems like a 555 is approprate. However, can it be done with just a LM324N since I have one already? Now for the oscillator we can cheat: charge cap with set current, but drive discharge directly from microcontroller. This way the frequency is exact but the amplitude depends on the current. Using a comparator input, this can be done in the PIC. How fast can a PIC respond? Can the comparator out be used to drive the discharge directly? It seems so. Entry: Non-compensated Date: Sun May 11 14:37:25 EDT 2014 How much harder is it to do all the compensation in software? The only dependency is temperature. If there's a way to measure temperature, it might be a lot simpler. Might need more bit depth though. To compensate an oscillator should be straightforward. As long as the frequency changes, a continuous estimate / control can be made of the offset and slope. Any other control system is harder without influencing the behavior. E.g. for a filter it's possible to track the self-resonance frequency, but only if the circuit is made to oscillate. The following strategy seems best: - Thermally couple all transistors, otherwise each circuit needs to be calibrated directly. That only works for an oscillator. - Perform one-time calibration of all transistor offset parameters. - Perform continous measurement on the oscillator(s) to determine T - Given T from the oscillator calibration, calibrate other parameters. Entry: Is offset still temperature dependent? Date: Sun May 11 15:02:49 EDT 2014 Offset depends on reverse saturation current I_s, so it doesn't seem that in the 2-diode approach there should still be temperature effects. Entry: For thermally coupled transistors, what else is necessary? Date: Sun May 11 15:23:23 EDT 2014 - Perform measurment of I_s / offset for all transistor in coupled set. Store this in EEPROM. - Use fixed high / low voltages to set current range. Entry: Two coupled NPN 2N3904 transistors + resistor divider Date: Sun May 11 15:37:25 EDT 2014 Assumption: Using two thermally coupled BJTs at the same V_BE, the current ratio will be constant, but not equal to one. To calibrate, two things need to be done: - Constant component offsets - Temperature. To "set the stage", build two reference rails to set max and min references to be used in the DAC. For a 3.3V supply e.g. from a zener from 5V, a ratio of 12-1-2 seems to be the right range. With standard component values this will be: 120k 10k 22k -> 152k 1 0.21 0.14 3.3V 0.69V 0.47V Let's simplify that to 100k 10k 22k -> 132k Note that using a zener is maybe not the best approach. These are specified at 20mA which is quite a lot, and they're not very precise either. Best to use a linear regulator and decouple at the 32k tap. Another one: how to limit the current at the high point? Probably best to leave about a 10x current error margin or 60mV. Note that is only 2% error in the resistors. Maybe best to stick to transistor biasing? So this is a bit dangerous. Can be mediated by not driving the transistor in full scale during calibration. Probably not a problem since the circuit is supposed to run with a digital control loop, but it feels very wrong to amplify errors like that.. The essential thing to keep in mind is that V_be = kT/q log(I/I_s). Knowing that T can vary about 10% in typical applications, the resulting current difference is quite large. Relative difference I_A/I_B = exp( (V_BE / V_TA) (T_B - T_A) / T_b) ). Or exp( 25 * DT/T ) Scaling of V_BE is just proportional to T. Alternative to resistor divisors is zener biasing. I still need to get a good idea of zener characteristics. Entry: Next: EIDAC Date: Sun May 11 19:05:20 EDT 2014 Two channel "lifted" MCP4922. Voltage rails from 3V3 reference. 2 thermally coupled TO-92 NPNs (2N3904) Smith-trigger analog oscillator (see LM324N datasheet) or PIC comparator oscillator. Entry: Transistor array Date: Sun May 11 23:25:08 EDT 2014 https://www.intersil.com/en/products/space-and-harsh-environment/harsh-environment/transistor-arrays/HFA3096.html Entry: Current Mismatch Date: Mon May 12 00:16:31 EDT 2014 The two 2N3904 I glued together, with R_C = 10kOhm matched and base connected give: 3.13V (regulated by opamp) 2.38V that's an error of 1.31 or 0.27 V_T or 6mV So, while the error in current can be significant, the offset itself isn't very large. The current seems to be still temperature dependent though it's not clear if this is just due to bad thermal coupling between the two transistors. It's clear that the effect is larger touching one of the two separate. One decreases the other increases the current. If a commercial matched pair[1] advertises 2mV offset (8% current mismatch), that 6mV doesn't seem too bad. As long as temperature drift is under control this can all be compensated by frequency measurements of oscillator/filter circuits. [1] http://www.nxp.com/products/bipolar_transistors/general_purpose_bipolar_transistors/matched_pair_transistors/ Entry: 1/3 DAC and 2/3 DAC_REF ? Date: Fri May 16 20:44:32 EDT 2014 Did I loose some notes? Basically, use a Vcc -> R -> diode followed by a buffer as REF voltage for a DAC. Send DAC output to a summing amp with 1R coming from REF and 2R coming from DAC. Summing gain set to 1/3 DAC, 2/3 DC (e.g. just a buffer). This should give ballpark voltage levels. As long as OSC/CONTROL transistors are thermally coupled, digital comp can be used to calibrate the pair. Entry: Looking for a good ISR structure on PIC 18F4550 Date: Sat May 17 11:46:49 EDT 2014 Problem is that there are two high priority interrupts. The low priority one (USB) should be easy to handle correctly. The fun part here is that it is quite time critical, so probably requires some instruction tweaking. Critical interrupts: - Comparator - DAC SPI out (timer?) It's ok to add a little delay to the DAC SPI out. However it would be great to do any comparator magic in HW. First need to look at how the comparator works, and how it combines with capture-compare. To use the comparators to create a sawtooth wave charging a capacitor with a constant current. Some remarks: - Set up to monitor voltage over capacitor compared to 2/3 V_DD / V_REF+ via internal voltage ref. There are 16 steps here which gives some amplitude control. - On interrupt: question is if comparator output can be used to discharge the cap. That would give best performance, but without hysteresis is quite unpredictable. An analog time delay on the input is maybe enough. - Integration cap probably needs to be buffered before going into comparator input. DS mentions R_S < 10k. There's 0.5uA leaking current which definitely puts it near the desired range (10mA - 10uA). Note this is also a problem for any opamp follower (LM324N has 45nA). - Picking a scale: what about keeping it simple and map uA to HZ? This as 20mA at 20kHz. It does mean that discharge currents at high frequency become quite large. - Picking a discharge method: is a NPN transistor good enough? Should it be a FET? Can it be a PIC pin? Probably not a good idea since it's a surge current. - Add histeresis with an external resistor network. This allows the interrupts to be used just for timing, but control remains in hardware. Base this on the reference voltage if possible. Entry: Comparator + software discharge Date: Sat May 17 13:27:06 EDT 2014 The path with least external components is the software reset path. The way to go here is to make the ISR fast such that the time from interrupt -> discharge is fast. Note that comparator can still be routed out for use in analog circuit. A simple way might be to preset LAT to 0 and switch the comparator input pin to digital out using one or two bit set instructions, e.g: TRIS <- 0 save timer clear interrupt bits delay... TRIS <- 1 RETFIE This requires the input to be unbuffered, so the 500nA leakage current becomes important. From the pov of response it doesn't seem faster then just setting a dedicated discharge pin. isr: LAT <- 1 to start discharge switch comparator reference save timer clear COMP IF wait for full discharge (2nd comparator?) switch comparator reference LAT <- 0 Reference settling time becomes important. Response time is 400ns max, 150ns typ. At 12MHz cycle an instruction is 83ns, so 5 cycles should be enough. What is R_ON for the output drivers? Essentially we just need to pulse it long enough. Might need to just try it. So in principle, this is the approach: - Comparator triggers -> start discharge - Do bookkeeping - Add fixed delay if necessary - wait for comparator output to settle Entry: Capacitor / current dimensions Date: Sat May 17 13:54:47 EDT 2014 Main restrictions: - PIC comparator input leakage: 0.5uA, (0.045uA for LM324N). - PIC driver impedance: 44Ohm. Ballpark: 1mA per Hz full scale (2/3 V_DD = 2.2V). 20mA -> 20kHz -> 50uS C = I T / V. (/ (* 0.02 0.00005) 2.2) 4.5e-7 450nF. Driver output impedance: Z_OUT is 28 to 44 Ohm. That's an RC time of (* 44 0.45) 19uS or 50kHz. Way too high. This needs a driver. To get a good sharp edge at 20kHz the discharge current should at least be 10x the charge current. Probably 100x is better to not cause too much frequency deviation. This is 2A spread over 50ns. Can a 2N3904 take this? Maybe best not to worry about this. Just drive it at 2A / 300(beta) = 6 mA base current or (/ 2.6 0.006) 470 Ohm. Seems the 2N7000 mosfet is going to better here: datasheet mentions 2A pulsed current is OK. (see next post) Conclusion: just use a 2N7000 at 3V3. The RC time is going to be around 3uS which compared to 50uS for 20kHz is quite alright. For frequency control, this can be taken into account but probably doesn't matter for f > 500Hz. How long to keep it on? Let's say about 5 uS. That's (/ 5000 83) 60 cycles. Might be better to use ISR for switching it on and off. Both comparators can be used. Entry: 2N7000 R_DS on Date: Sat May 17 18:24:49 EDT 2014 For the 2N7000: R_DS = 2.3 Ohm V_GS=3.3V R_DS = 1.6 Ohm V_GS=5V So at least at 3V3 it's more than an order of magnitude better than the PIC output drivers. RC time is (* 2.3 0.45) 1uS. I guess that's good enough. Let's try a couple more to see the variability. 6.3 4.1 6.3 2.3 Looks like the first one was a good one. Entry: ISR: one or two comparators? Date: Sat May 17 18:30:59 EDT 2014 Discharge pulse takes too long: 60 cycles. So this either needs 2 comparators (like a 555) or a timer interrupt to stop the discharge. How to dispatch on the comparator interrupt? One of the phases is not needed. How to ignore it fast? State is from: CMCON<7:6>, so that's BTS, RETFIE. Let's see... If the discharge transistor is activated as the first instruction in the ISR, it's probably going to pull the voltage below the comparator's threshold pretty quickly, so every time it goes over just be stupid and initiate a discharge sequence: - LAT <- 1 - TMR <- delay - clear IF If then due to noise this gets called multiple times, it's not an issue: it will just reset the timer. Timer ISR is: - LAT <- 0 - clear IF This looks pretty simple. Both interrupts need to be multiplexed in software, probably best to check the comparator one first. if CMIF if TMRIF Actually, turning the pulse off can be done using the output compare module. Entry: Capture / Compare Date: Sat May 17 19:34:40 EDT 2014 Since we're already creating an interrupt when comparator is triggering, the capture is easy to do manually. If there are no branches before the manual capture, there will only be a fixed delay. Capture mode can be used to measure the frequency of the other signal, translated to square wave. Triggering on the rising edge, it can be switch to 1x, 4x or 16x depending on expected frequency. Compare mode can be used to create fixed width pulses. Maybe interesting: using combinations of set/reset/toggle, it might be possible to use the output compare to make more flexible binary waveforms. Entry: 20mA is too much Date: Sat May 17 20:23:16 EDT 2014 If we drop an order of magnitude in current, from 2mA - 2uA, the LM324N leakage current (0.045uA) is still small enough. Discharging the cap with an 2N7000 will go 10x faster (6 instructions instead of 60) making the code simpler. I tried to get the reference voltage using a diode but that doesn't seem to be a good idea. Just use a 2N3904 as a diode. So trying in the order of 1mA (charging 47nF cap through 2k2 from 3v3). The discharge is pretty fast: spot on 0.5uS as expected. The buffer is slew-rate limited to 12uS. Entry: Low side charge? Date: Sat May 17 20:58:55 EDT 2014 Problem though: EIDAC only has a sinking current source due to GND level reference. The NMOS can't properly discharge a high-side cap. Does this need a current mirror? Rather not as it adds another source of current mismatch. PMOS equivalent? See [1]. TP0610 SOT-23 ZVP3306 TH, $1 ZVP2106A TH, $1 BSS84 SOT-23 DMG1013 SOT-23, $0.03 (DMG1012 N) [1] https://groups.google.com/forum/#!topic/sci.electronics.design/og2iI9I1IzM Entry: What needs to be done Date: Sat May 17 21:39:55 EDT 2014 - setup comparator: threshold = 2/3 V_VDD - enable interrupt - isr = LAT <- 1, clear IF, LAT <- 0, RETFIE - test on scope - add nops or output compare. Forth Extra (done): - enabling fast interrupt? - compiling into isr? Entry: About that PMOS Date: Sun May 18 20:48:22 EDT 2014 So... Because GND-ref it's easier to make a sinking EIDAC. This makes the sawtooth charge from 3v3 down. I used a 2N7000 NMOS for discharge, but don't have a PMOS. Why not use a 2N3906 PNP for discharge? I used the NMOS because of large peak current. Can the PNP take peaks? Or: what PNP can take peaks? Let's just assume this is not a problem and fix it when things start failing. Discharging 45nF can't be that hard. From [1]: BJTs are not components that can tolerate high current densities; you're not allowed to average the current over any arbitrary period of time, because destruction mechanisms exist that have nothing to do with thermal damages. So, measuring on the scope. 2N7000 NMOS is about 0.5us, also with 1k resistor. 2N3904 NPN is about 1us. Much slower with 10k resistor: NPN 3.5us, NMOS 1.5us. ( EDIT: I missed that 22k pulldown! ) So the PNP at 1us, how much current is it taking? Slop is about 3V / 750ns or 1V/250ns or 4V/us. C = q/V = I*DT / V -> I = CV / DT (* 0.045 4.0) -> 180mA. That's really ok. So maybe best to pick a source resistor to keep the rate down. [1] http://www.diyaudio.com/forums/solid-state/88122-pulse-current-survivability-small-bjts.html Entry: Multiple control voltages Date: Mon May 19 01:20:45 EDT 2014 Maybe it's good to use the 2-channel dac to control a couple of channels through sample & hold? Update rate is quite high so 8 channels is not a problem. This would allow one channel in the dac to be dedicated to temperature measurement. Something like LTC1391[1]. Another thing to try is to use a multi-dac like LTC1665[2], and use some kind of multiplication setup to get to higher or logaritmic precision, e.g. one for octave cal, one for octave, one for relative within octave. [1] http://www.linear.com/samples/LTC1391 [2] http://www.linear.com/samples/LTC1665 Entry: Schmitt-trigger Date: Mon May 19 19:40:09 EDT 2014 There doesn't seem to be a good way to handle hysteresis automatically in the PIC except as a consequence of how to handle the code. The oscillator itself could actually just be driven completely in an analog way, using a 1/3 - 2/3 Schmitt-trigger. Then if necessary, the I/O can be reconfigured and drive the discharge manually. I believe the comparator output is even asynchronous: "... multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator." Because of loading, it's probably necessary to buffer the output. Trouble there is slew rate. By the time the buffer catches up, the saw will have discharged past the 1/3 mark. Maybe best to take the input of the comparator behind the opamp as well, so PIC knows the buffered signal. TI LM324N spec says 0.5 V/us so it will take about 4uS to ramp down. I guess that's still plenty fast for audio but causes a 10% frequency drop at 25kHz. It can be made faster by lowering the threshold voltage through playing with the resistor values. EDIT: So it basically works, after placing an inverter in front of the transistor to get the right polarity. Could do this in the PIC but both polarities are necessary, or a different resistor network needs to be constructed. So interrupt is working as well. Nice to see the jitter from the comparator output wrt a pulse sent out from the ISR. EDIT: Works better using a non-inverting ST. Entry: Discharging a cap from 3v3 using a PNP Date: Mon May 19 20:16:44 EDT 2014 It's a strange situation because current flows into the 3v3 line. Since the surges is in the order of 200mA, maybe this can lead to problems? EDIT: no of course not. No current flows into the 3v3 line. Current flows out of the cap down through the PNP and back into the cap -- exactly the same as in the NPN case. My intuition about the NPN case was wrong though: no current is flowing into the ground either! Entry: Biasing OTAs Date: Fri May 23 12:12:18 EDT 2014 I have a bunch of LM13700[2][3] here waiting to find their destiny in a voltage/current controlled filter or oscillator. The EIDAC circuitry is done (compensation software still TODO) but at least the road is open to start to really experiment. I'd been thinking about using a current mirror to drive the 2 OTAs necessary for a SVF or SK style filter, however looking at the Korg schematic[1] it seems that driving both OTAs from the same control current is possible: since the input behaves the same (same current mirror circuit), they can be wired together. Makes me think if they can be driven directly from the EIDAC as well. I'll need to think about protection in that case. Don't want to blow up the OTAs one after the other. Problem is also that the MCP4922 in buffered mode has a 2x gain selectable in software. I can see that going wrong... Maybe best to keep it unbuffered? [1] http://www.timstinchcombe.co.uk/index.php?pge=korg [2] http://en.wikipedia.org/wiki/LM13700 [3] http://www.idea2ic.com/LM13600/LM13700.html Entry: Parallel DAC vs multiplexer Date: Fri May 23 22:06:10 EDT 2014 Problem with multiplexing DAC outputs is it needs a separate break/make sequence for the mux, giving 3 commands over the SPI bus, probably reducing speed quite a bit. Unless the mux is controlled digitally like a MAX336. Let's start looking for multichannel DACs with at least 12 bits. Entry: Thermally coupled NPNs Date: Fri May 23 23:44:40 EDT 2014 Not to forget that a multi dac still this needs one NPN per channel, best matched in temperature. So probably also a multi-transistor array. Where to get those? Something like a CA3081 array[2]? Or CA3046. Some newer parts like DMC50601[3] or one of the NXP dual transistors BC846, BC847[4]. Other: MPQ3906, MMPQ2907A, MMPQ3904[5] (4x - multi chip?). One that stand's out is THAT300[6], mouser distributes[7]. Multi arrays are expensive or and duals are not very useful. It might be better to stick with standard components and find a way to couple them in temperature. What about using power transistors instead? They can be hooked to a heatsking much easier.. Cheapest NPN in TO-220? TIP31C ($0.2). They're not cheap either.. Probably best to find thermal glue[8]. EDIT: There's also the TI LM3046[9] which is a replacement of the CA3046. Together with some duals for current mirrors this is the solution I'm looking for: one of the transistors can be used to produce a DAC V_REF, with 4 remaining as EIDAC channels. [1] http://www.linear.com/parametric/Digital-to-Analog_Converters_%28DAC%29#!cols_1049,1050,1056,1054,2234,1059,1031,1367!s_1050,1!gtd_!1049_%3E=12!1054_Serial%20SPI [2] https://www.futurlec.com/Linear/CA3081Npr.shtml [3] http://www.digikey.com/product-search/en?mpart=DMC506010R&vendor=9 [4] http://www.nxp.com/products/bipolar_transistors/general_purpose_bipolar_transistors/general_purpose_transistors/double_transistors/ [5] http://www.fairchildsemi.com/pf/MM/MMPQ3904.html [6] http://www.thatcorp.com/300-series_Matched_Transistor_Array_ICs.shtml [7] http://de.mouser.com/thatcorporation/ [8] http://www.newark.com/arctic-silver/aata-5g/adhesive-thermal-syringe-5g/dp/71T6886?CMP=KNC-GPLA [9] http://www.ti.com/lit/ds/symlink/lm3046.pdf Entry: VCA Date: Fri May 23 23:49:46 EDT 2014 Might be easier to use a VCA chip instead of the LM13700. Or not... Impasse. Time to build stuff. Tuning osc -> solvable. Tuning filter? Tuning VCA? What about not solving that problem and relying only on heatsink coupling. Entry: Synth arch? Date: Sat May 24 00:29:18 EDT 2014 - Two independent sawtooth oscillators (two comparators) - Unlimited square/pwm/... - VCF (freq + rez) - VCA -> 5 DAC outputs. Possible to side-step VCA by using only envelopes. I want too much at once.. Need incremental approach. 1. Tune the oscillator 2. Use the other channel to make a filter 3. Find a way to tune the filter Entry: Capture/compare Date: Sun May 25 14:24:24 EDT 2014 Might do input capture manually from the comparator change interrupt. Basically, read TMR0L then TMR0H Section 11: TMR0 module: TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. So to get an update: - read timer - push - subtract previous - shift / multiply - add to accumulator - pop - store previous Probably best to keep the timer rolling. If the input capture is not used for anything, this can actually be split into a top and bottom half, with top half just initiating the capture and the bottom half performing the update. Entry: Kalman filter Date: Sun May 25 14:29:08 EDT 2014 Since there are a couple of variables that need to be estimated, it might be good to perform a proper kalman filter state estimate. Entry: Current modular Date: Mon May 26 02:30:53 EDT 2014 Idea from the past is to use currents as signal carriers. Some problems: source/sink distinction + no fanout - but free fan-in. Entry: Maxim DACs Date: Mon May 26 02:38:47 EDT 2014 http://para.maximintegrated.com/en/search.mvp?fam=precision-dac&527=4|5|6|7|8&528=8|9&374=Serial%20-%20I%3Csup%3E2%3C%2Fsup%3EC|Serial%20-%20Other|Serial%20-%20SPI Entry: Real modular? Date: Mon May 26 02:44:38 EDT 2014 Starting to look attractive to build a real modular using standard interfacing. Entry: Modules Date: Mon May 26 02:56:07 EDT 2014 Thinking about placing modules on separate boards, it seems best to put a quad sawtooth on a separate board using a quad comparator and current sinking inputs. Or a dual saw using a single LM324N. This allows separating out the dac board (4 EIDACs). Entry: Inverting / non-inverting Schmitt trigger Date: Mon May 26 11:51:56 EDT 2014 Current saw circuit requires an extra inverter to drive the transistor. The ST in the circuit is inverting: if V < V_low the output goes high, if V > V_high the output goes low. It needs a non-inverting Schmitt trigger. [1] http://en.wikipedia.org/wiki/Schmitt_trigger Entry: Updated to non-inverting ST Date: Mon May 26 18:00:51 EDT 2014 Works - recorded in schematic. Also had a measurement problem attaching probe to cap directly. Entry: How to tune with trimpots? Date: Mon May 26 18:02:50 EDT 2014 - Tune ref at DAC=255 - Tune weight at DAC=0 Same goes for digital tuning. Entry: Next Date: Mon May 26 18:18:39 EDT 2014 - PIC freq measurement - Use CA3046 Entry: CA3046 vca Date: Mon May 26 18:20:14 EDT 2014 http://hem.bredband.net/bersyn/VCA/ca3046%20vca.htm Entry: temperature and v_be mismatch - final words? Date: Mon May 26 21:04:56 EDT 2014 Assumptions (seem to be correct): * I -> V_be -> r x V_be -> I is temperature stable as long as transistor are thermally coupled. * Offsets are static and can be calibrated at production time as long as a significant margin is used. -> This is different from "real" analog gear where either good matching is required, or trimpots are used to compensate offsets. Why is this "averaging" circuit not used in more classical analog designs? Dependence on opamp offset maybe? No, that can be compensated for. Yes, what's wrong with it? Entry: Filter Date: Tue May 27 00:02:13 EDT 2014 The diode ladder might be a stretch to run on 5V. What about combining the EIDAC biasing to drive a single-ended ladder and use opamps to perform the feedback? Googling gives[1]. Not really what I expected. Why the stacked ladder? (* 8 0.63) So some questions: - C vs I_c, what's a good range? - Why 3 "headroom" diodes? Might be too much for 5V op. Wrt headroom, current guess is that there has to be *something* there to avoid the point to be grounded. A diode is best since a resistor wouldn't have enough dynamic range. A couple of diodes raise the resistance so give more voltage swing. Found some more links[3]. The interesting part in that schematic is the way the signal gets coupled in through the "ground" connection of one of the caps. [1] http://www5b.biglobe.ne.jp/~houshu/synth/Vcf0111.gif [2] http://www5b.biglobe.ne.jp/~houshu/synth/ [3] http://www.experimentalistsanonymous.com/ve3wwg/doku.php?id=diode_ladders (/ 1.0 (* 6.28 (/ 0.026 0.001) 0.00001)) Entry: Feed V_BE back to ADC to serve as thermometer Date: Tue May 27 17:34:26 EDT 2014 It's possible to create stable current from the EIDAC, but the dynamic resistances in a diode filter still depend on temperature. Entry: Digging in the old box Date: Tue May 27 21:59:58 EDT 2014 Many ideas just come back. - LM324 is a "horrible excuse for an opamp" Though TL074 needs a lot of headroom (1.5 to 3V both sides) - Using MAX232 to generate analog +-12V Can deliver a couple of mA (short is 10mA). Very dirty power as well. Is there another way to get there? TODO: get a good +-12/15V power supply for analog - Revive the 9V stomp box. I've got a lot of enclosures still. - The peak squashing circuit! - PWM resistors - The scroll grid circuit; might be interesting together with CV control. - Modular system: fixed 1k output impedance, summing input amps. It would be great to figure out how to allow for bi-directional current outputs. - Stacking DAC, PWM and SD - Exponential converter, though no sign of a relative one (that was a lucky shot). - CD4049UBE current mirror / datong clipper. - Gilbert cells - R/DD (double diode) for reference + SD aimed at 50% of the mid range to avoid low frequencies. that might actually work Entry: Calibrated analog? Date: Wed May 28 01:02:11 EDT 2014 Instead of keeping the control in the digital domain, what about making self-calibrating pure analog modules? Entry: FPGA? Date: Wed May 28 10:02:10 EDT 2014 - S/D based approach - Equalizer Entry: Counter Date: Wed May 28 10:03:24 EDT 2014 What about using the counter to measure frequency averages? Might be less intensive as it allows to run computations at a fixed rate. Is less precise though. Entry: digital envelopes Date: Wed May 28 13:42:21 EDT 2014 http://www.soundonsound.com/sos/feb08/articles/dsiprophet08.htm Entry: 25 x CA3046 arrived Date: Thu May 29 18:41:43 EDT 2014 I hooked up the ref + osc to the matched differential pair. There is some temperature sensitivity when touching the package but definitely better than the ad-hoc thermal coupling gluing the backs of two TO-92 together with crazy glue. Now checking if there's drift once I leave it alone. I did notice that at 2.5mA the V_BE was substantially higher: 750mV as compared to 670mV for the 2N3904. So time to move on to controlling the filter. Entry: Building a filter Date: Thu May 29 18:50:09 EDT 2014 Let's first string together some diodes. Entry: Coupling signal/feedback into the filter section Date: Thu May 29 23:32:40 EDT 2014 3 points: 1) RC to end of ladder 2) RC to beginning of ladder (at bias collector) 3) as small signal part of bias input I tried 1) which has the disadvantage of coupling into a low resistance at high current/frequency. Signal looks ok but a little distorted. Let's try coupling into 2) Coupling into 3) is a high-impedance / current coupling as opposed to low impedance voltage coupling, so have to figure out what the result of that is. Coupling into 2) is problematic because that point is at one diode drop below V_cc so opamp can't deal with it. So now I have it coupled into the base of the bias transistor, which +- works. Trying to make a non-inverting amplifier with DC gain of 1 but that doesn't seem to work (bypassing the resistor from - to GND). Maybe best to AC-couple it into one that's biased around 1.5V Go over these scenarios again with a fresh mind.. Some conclusions for now: - collector is high impedance, so might be best for input - terminating diode is low impedance: best for output? AC couple into 1M/1M bias network? Entry: Current mirror BCV62 (PNP) / BCV61 (NPN) Date: Fri May 30 23:46:59 EDT 2014 The BCV62 is the cheapest current mirror I can find @ digikey. $20 for 100, comparable to CA/LM3046. Current mismatch max 30%. Counterpart BCV61 about 30% more expensive. These would work as: - current mirrors for driving OTA from NPN EIDAC - Straight NPN/PNP EIDAC Building a PNP EIDAC needs some thought as I'd have to use a ground-referenced DAC, so the same trick can't be used. Probably best to avoid that and use a current mirror. Entry: Diode filter pinned between voltage and current source Date: Sat May 31 02:44:35 EDT 2014 EDIT: SOLUTION: Place ladder in between a voltage source and a current source. - DC voltage bias + AC input at voltage source side, - DC current bias + AC output at current source side. Making the dual of the one-pole filter at [1] it seems clear that the signal needs to be injected at the V_cc side in my circuit. The AC voltage source acts as transformer coupling. How to do that then? Wait.. The diode string can just be fed from a summing amplifier that produces a DC offset near Vcc + the AC voltage. In my circuit this needs a rail-to-rail opamp (e.g. MAX4167, MAX494, MCP6244), or a lower DC voltage, say 2V. Is there enough room to run the diodes? With just 3 diodes at a lower current that should work. Or an emitter folower with an AC signal coupled in. [1] http://www.experimentalistsanonymous.com/ve3wwg/doku.php?id=diode_ladders Entry: Diode ladders vs. single leg Date: Sun Jun 8 14:21:04 EDT 2014 I've been trying to figure out why one would use a ladder instead of a single leg. Here's a difference: In a ladder, when the control current changes and the diodes are matched, there is no resulting transient current through the capacitors. In a single leg filter, the caps need to charge/discharge when the DC operating point changes. Now, is this significant? If a step is applied to the control current, the voltage will step as well, but with less amplitude (logarithmic) and filtered through the capacitors. Guessing it will still sound like a filtered discontinuity, i.e. ring at high resonance. EDIT: This is a very clear pop. Annoying to the point of being useless. How to remedy? Entry: 4 pole single ended diode filter on breadboard Date: Sun Jun 8 17:44:00 EDT 2014 Tweaking the resistor values a bit, it seems to do what it's supposed to. Verified that a large cap in the feedback circuit is a problem when stepping the voltage: hits saturation and sound drops for a bit. Making that cap smaller transforms the drop into an audible click. Also, there's a lot of bleedthrough from the digital communication to the analog path. Maybe best to start separating the analog and digital supplies and ground. So, 2 problems: - digital bleedthrough - CV bleedthrough due to bias voltage change (diff amp?) Playing a bit more, it seems that sending a hotter signal is probably a good idea for this kind of filter - s.t. normal out is just a little under self-osc amplitude. Since it's quite noisy and has a lot of bleedthrough, let's go for "character" instead :) Some more remarks: - I'm actually not using a cap from SAW->Filter. Since the bias is constant, this is OK. - The pop might be mostly due to the coupling cap still used in the feedback path. I wonder if it's ok to leave that one out as well, i.e. allow DC to come in but make sure it's much less than the set DC. This would then leave only a single cap in the circuit to set the HP pole. Basically, if the current is low, the bias voltage at the bottom of the ladder is low. This gets fed back to the top of the ladder bringing the voltage down a bit. It seems that as long as the gain through the loop is small enough, there should be a set point that is stable. Is there a way to completely cancel the voltage drop at the collector? No, but it's possible to spread it out evenly by setting inverting gain to 1/2. Trouble seems to be that there is very little voltage headroom to add more than 5x gain at that point. Distortion happens before loop gain goes to 1. - What about placing a cap on the CV? Making it slower should make it easier for the cap inside the feedback loop to follow. So basically it works when the signal level in the feedback loop is kept in check. However, this requires large coupling caps and those cause bleedthrough. So all-in-all this circuit is not good for sharp CV transients. Might be good for other things though. Entry: Off the charts.. Date: Sun Jun 8 20:20:19 EDT 2014 So trying to get the cap-less feedback to work with a 1/1 DC feedback, and I'm running into all sorts of crazy sounds setting the feedback gain and bias voltage. Might be usable! Entry: Ladder Date: Wed Jun 11 16:58:44 EDT 2014 Trying out a new design with a second string of diodes used only to provide a bias reference. Problem is that these are not low-impedance DC ground. Does this need to be fed with a differential signal, or is the networks still capable of shifting phase? I'm guessing yes since there is a nice symmetry. Let's just build it. Entry: Capacitors for audio Date: Wed Jun 11 18:41:02 EDT 2014 Class 2 ceramic capacitors might be problematic[1]. I've ran into this before. (re-googling: [2]). So what kind would be good? Dave mentions in [1] that "class 1" capacitors (only low-value e.g. <1nF) are quite good. NPO, COG. Also, ceramics are microphonic, so probably not good in the signal path. Mylar (polyester film)? Metal film? Same thing? Hmm... not a simple thing apparently. [1] http://www.eevblog.com/2014/06/07/eevblog-626-ceramic-capacitor-voltage-dependency/ [2] http://quadrevisionspot.blogspot.com/2010/12/what-are-best-capacitors-for-audio.html [3] http://en.wikipedia.org/wiki/Types_of_capacitor [4] http://electronics.stackexchange.com/questions/69919/ceramic-vs-film-capacitor-which-one-is-preferred-in-audio-circuits Entry: Envelopes Date: Wed Jun 11 20:28:23 EDT 2014 I'm not sure if digital envelopes are a good idea. Especially for VCA, it might be interesting to allow for signal-modulated gates, i.e. avoid aliasing / digital jitter in the start of a note. Entry: MCP6244 GBW 550kHz Date: Sat Jun 14 11:28:02 EDT 2014 This is a low power opamp with reduced GBW. That might be a problem since I do need a bit of gain at full audio bandwith for resonance. However, gain can possibly be spread over two opamps. Entry: Dinosaur den - analog synth Date: Wed Sep 10 22:03:14 CEST 2014 [1] https://www.youtube.com/watch?v=rsJHP46sJlQ#t=780 Entry: I want to twiddle knobs Date: Thu Oct 16 16:32:19 EDT 2014 So let's get started building some things: - Midi control for monotron. - Paia with frontpanel (about to order box) - Frontpanel for new synth (ordered eurorack case) - Rotary Encoder Manifold Explorer (REME) Entry: Euororack dimensions Date: Wed Oct 22 17:03:33 EDT 2014 - m3 x 6mm + washers Entry: Designing board Date: Fri Oct 24 17:38:01 EDT 2014 Basicly, it's time to move forward. I started thinking about adding the EIDAC to the pic dev board proto area but really that's probably more of a hassle. And it's not reproducible... Let's make a board. First iteration: no uC. I have plenty of PIC boards and probably would leave open the option to switch to a different kind. Who will fab it? New thing is Dirt Cheap Dirty Boards[2] But for now I do need shorter lead times[1]. [1] http://batchpcb.oshpark.com/ [2] http://dirtypcbs.com/ Entry: KiCAD Date: Fri Oct 24 18:04:48 EDT 2014 [1] http://www.eevblog.com/forum/open-source-kicad-geda/is-geda-more-usable-than-kicad/ Entry: Spice Date: Tue Nov 4 18:11:44 EST 2014 Two things I'd like to do: - Get spice to run from the schematics - Export netlist to Scheme for ad-hoc analysis Currently I need resistors, capacitors, voltage sources, diodes, BJTs and (ideal) opamps. [1] https://wiki.ubuntu.com/Intro_to_opamps_with_ngspice-gEDA [2] http://sourceforge.net/p/sdaaubckp/code/HEAD/tree/single-scripts/ngspice-opamp-test.sh Entry: Next Date: Sat Jan 10 21:18:56 EST 2015 Get the filter to work. Once that works, connect it to the PIC and create some control-rate modulations and pitch state machine. This needs some hands-on reconnecting.. Entry: Hybrid Date: Sat Feb 13 14:21:24 EST 2016 CVs: only necessary for VCA and FILTER. Oscillator and LFOs can be digital. Works both for PIC+external dacm and STM32F103 with internal 2-channel dac. How to build an analog VCA? This would be just a differential pair using one of the temperature-coupled transistors on the transistor array. Entry: spice Date: Mon Feb 15 00:33:01 EST 2016 http://wiki.geda-project.org/geda:csygas http://wiki.geda-project.org/geda:ngspice_and_gschem http://www.seas.upenn.edu/~jan/spice/spice.overview.html http://www.johannes-bauer.com/electronics/gnucap/ Entry: VGA Date: Tue Feb 16 11:14:58 EST 2016 As for VCA I was thinking about just a common base pair, pulled by an EIDAC. Here's something to start from: http://experimentalistsanonymous.com/diy/Schematics/Amplifiers%20and%20VCAs/Paia%202720-1%20VCA.gif Entry: Spice BJT models Date: Tue Feb 16 14:03:53 EST 2016 Not entirely clear how to add NPN models to a spice file so gnucap can simulate it. Q1 1 2 3 NPN Says 'Q1: can't find: NPN' Models are separate in spice files. Seems that this needs to be added in the schematic as an "A" (annotation?) block. [master] tom@tp:~/rai/spice$ apt-file find 2N3904.mod apt-file find 2N3904.mod geda-examples: /usr/share/doc/geda-examples/examples/TwoStageAmp/models/2N3904.mod So the component needs a value=2N3904 attribute. C 43700 45200 1 0 0 npn.sym { T 44300 45700 5 10 0 0 0 0 1 device=NPN_TRANSISTOR T 44300 45700 5 10 1 1 0 0 1 refdes=Q1 T 44300 45500 5 10 1 1 0 0 1 value=2N3904 } The schematic then needs a separate model box to trigger inclusion by gnetlist of the model file into the final spice file. C 53800 49800 1 0 0 gnucap-model-1.sym { T 53900 50400 5 10 0 1 0 0 1 device=model T 53900 50300 5 10 1 1 0 0 1 refdes=A1 T 55100 50000 5 10 1 1 0 0 1 model-name=2N3904 T 54300 49800 5 10 1 1 0 0 1 file=gaf/models/2N3904.mod } Entry: disable gschem logging window on startup Date: Wed Feb 17 12:14:17 EST 2016 root@tp:/etc/gEDA# git diff HEAD~2 HEAD system-gschemrc diff --git a/gEDA/system-gschemrc b/gEDA/system-gschemrc index c8a8707..d3dd2bd 100644 --- a/gEDA/system-gschemrc +++ b/gEDA/system-gschemrc @@ -410,8 +410,8 @@ ; later - NOT opened up when gschem starts ; (can be opened by Options/Show Log Window) ; -(log-window "startup") -;(log-window "later") +;(log-window "startup") +(log-window "later") ; log-window-type string @@ -441,9 +441,9 @@ ; ; Default is log_window ; -(logging-destination "log_window") +;(logging-destination "log_window") ;(logging-destination "tty") -;(logging-destination "both") +(logging-destination "both") ; text-size number ; Entry: VCF tweaks Date: Wed Feb 17 23:10:04 EST 2016 Assuming that basic operation is correct, and that the weird HF behavior is an impedance problem: How to tune the gains? Once that is done, tune the impedances. First step in tuning the gain, is to determine the small-signal transfer function of the diode/capacitor network. The point of interest is where the resistor/capacitor ladder reaches 180 degrees phase shift. What is the gain at that point, taking into account the input impedance of the diff-amp. What I want, is to compute sensitivities: - Impedances - Component value -> other signal property What I'm thinking though is to stop making this cerebral: bring back the iterative tweaking idea. Take the circuit, and translate it into a C program that computes the simulation output. No matter how much time it takes, and plot it / play it. Keep all parameter values parametric, and tweak them in the same way as other RAI interactive tweaks work. Once that works, other sensitivities would be simple to calculate, as derivatives of the whole function, or of some kind of accumulation. It is all functional. Keep it all functional and all that stuff should just work. Entry: LM3046 replacement for CA3046 Date: Sun Apr 24 09:47:55 EDT 2016 According to Old Crow http://www.oldcrows.net/ LM3046 still plenty. http://www.ti.com/product/LM3046 http://electro-music.com/forum/post-217868.html Entry: Synth: permanent setup Date: Fri Jun 2 11:15:31 EDT 2017 After seeing Chris Beckstrom's synth, I'm encouraged to "just build it, nomatter how it looks". Thinking about this a bit, what is needed is to find a good balance between solderless and soldered breadboard. Once it works, finalize it. Anything else should be pluggable. Socket all the key components such as capacitors. The setup, all with MIDI in and USB debug in. - Sheepsint, digital only - Analog eidac + saw + filter - STM32F103 - Raspi or beagle Entry: Analog synth: use PIC or ARM? Date: Fri Jun 2 12:04:08 EDT 2017 I'm inclined to drop it, because at least some DSP is going to be necessary to do the calib loops, and really, multiplications in staapl is not the way to go. The thing is that the pic synth can be its own thing. There is a lot of ground to still explore there, so let's keep it simple. For the calib loops, it makes more sense to do those in RAI, and use one of the cheap STM32F103 chips to do the DSP. Entry: PIC synth Date: Sat Jun 3 08:03:19 EDT 2017 While it's neat to have stand-alone midi, it's actually not necessary for development. So let's go back to USB midi. Once that is set up and hooked permanently to the mixer, more sounds can be created including modulators. The main issue is the multiplier for parameter transformations. So abstract that a bit more. Entry: Analog and PIC Date: Sun Jun 11 15:54:08 EDT 2017 Maybe it's not all so straightforward. PIC might be more interesting electrically, e.g. because of comparators, and also its small size. Entry: STM32 Date: Sun Feb 17 07:55:48 EST 2019 I've got the bluepills set up in a convenient way now. What's next? The controller for the analog board will need midi. Maybe set that up first? Entry: Clean square Date: Sun Apr 14 17:27:09 EDT 2019 Power an inverter from a cleaner supply. So how do you derive a clean reference signal from a dirty supply? https://electronics.stackexchange.com/questions/141312/clean-dc-power-supply-from-a-dirty-souce https://www.embedded.com/design/real-time-and-performance/4007179/Effective-use-of-filter-capacitors-to-clean-up-voltage-source-signals-in-portable-consumer-designs What about upconverting? 5V into a linear regulator is not much, but 5V to 12V and then bringing down to 9-10V might not be so bad. How is it done in the microbrute? They just use a 12V supply. I have a bunch of those, so let's not worry about it. EDIT: They take 12V, take it down to: 5V digital, which then fans out to 5V digital and 5V to derive a +12/-12 supply. I do not want to get into building power supplies. Build an add-on circuit to the microbrute, reusing power supplies. EDIT: Monotron also uses a 5V supply from an upconverter. Entry: What to do with the PICs? Date: Sun Apr 14 17:30:35 EDT 2019 Basically, USB sort of works, but it is not a good match for the PIC. It might be much better to avoid the issues and have the PC <-> Circuit bridge be handled by an STM32 running plain old C. Then use a reliable connection between the STM32 and the PICs. Entry: Microbrute schematics Date: Sun Apr 14 18:48:46 EDT 2019 http://hackabrute.yusynth.net/index_en.php?&arg=4 Entry: Building a synth Date: Sun Apr 14 18:58:13 EDT 2019 I don't need to build anything "normal". I want mostly to build the PIC synth for its uniqueness factor, and have some analog glue for it. It might be enough to just connect it to the microbrute. Do the same as with exo: have a setup always running. So what are the ideas to explore? - digitially controlled sawtooth - the minimal diode filter - PIC synth digital cleanup I think I should fist do mods, to get a bit of a feel for doing things incrementally. The chunks are too big otherwise. The monotron is a good starting point. It uses LM324 opamps, so I guess I can just add to that. Digital board: - blue pill, with bit-bang spi or UART to pic chips, able to reset the PIC chips. - level converters? PIC input should be 3v3 tolerant. Just use an array of bipolar transistors. Level shifter: https://www.adafruit.com/product/735 74LVC245 Since this is only for debug, can the PICs be placed on the same bus? Yes. Then I don't think I need a level shifter. STM 3v3 drives NPN, which inverts and converts to 5V. Pics each have 5V driving NPN, which inverts and converts to 5V. Yeah shared UART will be fine. EDIT: Eliminate the PICs in a first attempt. I think it is too much trouble. I do want to actually build something, not get stuck in a bunch of interface debugging. I've set up these STM32 devices already, now it is time for analog. For anything that needs cycle-accurate timing, use the FPGAs. It's time to move forward. The thing to learn is to not invest in specific architectures. ARM/32bit C and FPGA are generic enough to be future-proof. Entry: MicroBrute symmetric pairs Date: Sun Apr 14 20:30:27 EDT 2019 In the metalizer section. I first thought this was a matched pair, but it's not. It's used as a driver section: BC847BPN : PNP + NPN Entry: Tuning Date: Mon Apr 15 20:02:27 EDT 2019 http://item.warp.net/interview/aphex-twin-speaks-to-tatsuya-takahashi/ "same thing in the minilogue and the volcas too: the oscillators are re-tuned when they're not being used" Entry: Synth Date: Mon Apr 15 23:17:19 EDT 2019 I need to make a synth, publically. And it needs to be a digital one. At least at first. The analog work needs another decade to ripen. However in order to make that synth, I need to make my own one-offs to actually make music. Techno is my vehicle for exploring sound, and analog mods might be a great form of inspiration. Entry: 5V Date: Thu Apr 18 14:58:24 EDT 2019 So this is quite annoying. Either I use a 5V controller, or I use level shifters. I actually do have a level shifter board. So I've been flip-flopping between involving PIC or not. Today, I think again that it might be worthwhile. The reason being that there is working code. There's nothing like working code. Entry: PIC setup Date: Thu Apr 18 15:05:33 EDT 2019 What is needed to get the dev tools working again? It actually compiles using this: mzc v6.1.1 [3m], Copyright (c) 2004-2014 PLT Design Inc. Installed in /usr/local/racket-6.1.1 I guess this is good enough. EDIT: MIDI + audio wired in a semi permanent way. The next step (connecting it into exo) is a brainy one, so maybe not for right now. I think it's time to centralize next.txt Entry: First circuit Date: Thu Apr 18 19:20:32 EDT 2019 Should be a VCA + envelope. Maybe combined? This will give most bang for the buck. And drive it from a digital I/O. Entry: VCA / Env Date: Fri Apr 19 07:19:43 EDT 2019 How to make a VCA? I have some OTAs still. I'll need an exponential converter. There is a vca.sch EDIT: Apparently my setup broke. apt-get install geda This was missing ~/gaf link The vca.sch is a discrete current-sink controlled circuit. So what do I do next? I'm only interested in percussive sounds for now, so the EIDAC should work fine with some filtering on the drive circuit. Focus on the EIDAC? As that exponential relation is what is hard to do digitally. Can I port the EIDAC to STM32? The STM32F4 has two DAC converters, 12 bit. So not really an option unless buffers are used. I need way more channels. Entry: EIDAC review Date: Fri Apr 19 07:30:45 EDT 2019 The main idea is to use two transistors: - Q_REF to create a reference voltage V_REF from I_REF - V_DAC voltage is then a fraction of V_REF - V_SINK is created by adding an offset: V_DAC * 1/3 + V_REF I used a MCP4922 dual DAC for this, and LM324 opamps off of 5V. I think the PIC actually operates at 3V3. There are a couple of places to go with this: - external MCP4922 - internal DAC (STM32?) - FPGA-based s/d DAC For the FPGA there are a couple of options. Possibly simplifying the entire circuit. I will probably need a bunch of these, so it might be worth exploring. Entry: Axoloti Date: Fri Apr 19 07:42:46 EDT 2019 I have two (black) STM32F407VET6 boards Axoloti is STM32F405R6T6 Difference is? See ramblings://electronics/20170807-123156 FIXME: Restore notes linking. Entry: Many EIDACS Date: Fri Apr 19 08:05:03 EDT 2019 So assuming the exponential current controls are the way to go, let's find out how to make a bunch of them. CA3046 or LM3046. These have 5 transistors. One can be used as a reference, the rest as outputs. So that's 4 outputs. A quad daq might be more appropriate. E.g. MCP4728, though MSOP only. Another option is to use a sample & hold. But let's stick to what is there already. I have one MCP4922 left. Board can be built with room for a second one. Maybe order some more samples. Ok, did so. So this would be a bridge from SPI to current sink. This should fit on one of those small proto boards. Analog circuits can then be built on different boards. Entry: CA3046 Date: Fri Apr 19 09:00:40 EDT 2019 I can't find those. I bought a bunch. There are only 2 on the breadboard. Found the box. Apparently I had started sorting parts and what was in the metal drawer is unsorted. Entry: Synth host Date: Fri Apr 19 09:03:06 EDT 2019 Instead of messing with the microcontrollers, maybe use the BBB. It might be a better platform. Entry: Paralysis Date: Fri Apr 19 21:59:59 EDT 2019 So how to go about this? Solderless breadboard, dead bug, or through-hole solder breadboard? I need someting that can be made simple, so no turning over boards for sure. Maybe just solder side of through-hole breadboard + labels? I've never tried dead bug. What about flat bug? Then I don't need to add labels. I just hate this fucking combinatorial shit... I'm going to have to make proto boards, because breadboarding is going to take a lot of time. It's all slowly coming back to my why I don't do this! Anyway, I want to do dead-bug at least once just to get an idea. EDIT: I really fucking hate soldering. No. It's not the soldering. It's turning over boards. Do it all on the same side. Entry: Make prototyping more incremental Date: Sun Apr 21 10:36:28 EDT 2019 Does this just mean using larger boards? I.e. leave some room for extension? - no board flipping. This allows a large surface to be used. Can be as simple as putting copper up for the circle breadboards. - more space between components - stripboard vs. circular perfboard? settle on something! Entry: For the EIDAC? Date: Sun Apr 21 11:09:07 EDT 2019 Start by connecting a single the MCP to the uC in the test area, or even by adding a separate uC to the control board. Then write code for the DAC and test it on the scope. Do this incrementally in a way that is as stupid as possible, by just adding ICs to the board one after the other. I have to get over the premature optimizing part for the place and route. It is a show-stopping obstacle every time I approach the problem. Try to make local decisions in first iteration. The second step is an actual circuit board. So the main decision at this point is to use the "bench" uC, or to add one to the circuitboard. The former is definitely simpler, so start there. The first thing that's necessary is a power supply: 3v3 for the DAC, and probably an isolated 5V for the opamps. Entry: Power supplies Date: Sun Apr 21 11:20:01 EDT 2019 I don't want to spend a lot of time on it, so use something existing. Here are some options: - get 3v3 from the STM32 board, and use a separate supply to produce the analog voltage, e.g. the velleman kit - use the power supply from the eurorack case. just gut it for now, and replace it with another one. - take everything off of the delta1010 breakout box I think the Eurorack might be the best option. It has 5V also, which I can just bring down to 3v3. This needs a decision. I can't keep all the options open. There seem to be only two ways to go: - Monotron-style 5V analog - Eurorack style 5V digital and +-12V analog Where the latter can be replaced by any other symmetric setup. The former seems simpler, so for now forget about noise and just get the 3v3 and 5v from the STM32 board, keeping in mind that later the 5V should be the analog supply. Entry: STM to board interface Date: Sun Apr 21 11:53:59 EDT 2019 Ribbon with: - 5VA analog (currently just dirty USB) - AGND - 3V3 digital - GND - CS - CLOCK - DATA So 7 pins. AGND can be omitted for now and just use digital. Note that power supply noise might actually be beneficial in this case as it creates a little modulation in the frequencies. Entry: EIDAC revisited Date: Sun Apr 21 11:58:20 EDT 2019 It is enough to just stick with 2 DAC channels. With 4 output transistors, there can be some simultaneous driving, e.g: Entry: Drive LM13700 input diode directly? Date: Sun Apr 21 12:02:04 EDT 2019 EIDAC is current sink output, but LM13700 uses diode input for current. It might be possible to avoid some current mirror setup by driving diode PN junction directly. Problem is there is no thermal coupling. But that might not be needed if it can be tuned digitally. Maybe one of the LM13700 can be used as reference? EDIT: It's not just a diode input. I've seen the circuit before. Some kind of of current mirror with extra stabilizing feedback? However the CA3080 does have a diode input. Entry: STM32 controller Date: Sat May 4 12:49:38 EDT 2019 Context is currently refreshed after some excursion for work, so what can I do? I'd like to have a proper midi interface. Two ways to go about this: - Implement USB midi on cortex - Just use an ad-hoc interface over ttyACM for now I'd really like to have midi for sure. But this requires some changes in the bootloader. What about making a bootloader on top of sysex? Here's some example code: https://github.com/libopencm3/libopencm3-examples/blob/master/examples/stm32/f4/stm32f4-discovery/usb_midi/usbmidi.c Since this is no longer just a serial port interface, it might be good to write a completely new bridge. Though that is a lot of work only for so called elegance.. Let's just stick to serial ports, and use something like ttyMIDI or even just a special purpose jack client for interfacing. Yeah the whole point is moot. If there is translation anyway, just use an ad-hoc protocol to begin with. Find an application first. Then implement the protocol in whatever way makes sense. EDIT: So what I did was set up a framework in wavegen.c - 48kHz ISR - ETF dict interface Entry: Switch to STM32F103 Date: Mon Jan 27 14:25:24 EST 2020 Ok so maybe one day I get nostalgic for the PIC18 and will finish Staapl or port it to Haskell, but until that day comes I think it's best to switch to the current workhorse. MCP4922 Can operate on 3v3. Needs comparator. Does the STM32F103 have a ST input? Yes, so this could probably be used as interrupt. Entry: 909 kick Date: Tue Apr 21 16:42:49 EDT 2020 https://www.muffwiggler.com/forum/viewtopic.php?t=111119 I don't think I really need the analog one. Just figure out an emu in rai? Entry: zapper.txt Date: Wed Apr 29 10:13:45 EDT 2020 Found this in tom@panda:~/papers$ ls -la zapper.txt -rw-r--r-- 1 tom tom 648 Dec 10 2011 zapper.txt vocal zapper. paia. http://www.paia.com/vocalzap.htm#works gebaseerd op stereo/center reductie. weet niet of dit wel goed gaat werken. alesis http://www.alesis.com/products/VocalZapper/about.html 16 verschillende algoritmes. boy/girl alt/soprano/... left/right/center. waarschijnlijk zelfde aanpak als paia, met iets meer filtering.. duidelijk STEREO. review, waaruit blijkt dat het wel degelijk een subtractor is http://www.americanmusical.com/item--i-ALE-VZ--brand-9.html algoritme: fase canceller: in deel van spectrum waar stem zit: 180 shift. stereo in/stereo uit. oftwel: filtering op somsignaal, en laat verschilsignaal gelijk. Entry: reviving embedded synth work Date: Thu May 7 15:18:15 EDT 2020 There are two avenues: 1. ARM Cortex. The path here is quite straightforward. Probably should be Rust also. I need to get this set up so it can start producing sound fairly quickly. 2. Staapl I forgot when I last touched this. Even forgot where the logs are. I found some mention in staapl://20170603-095533 I probably won't be able to let this go considering the amount of joy it brings. I usually do get disappointed when I run into one of the old stumbling blocks. But at the very least let's get the board back up, and integrate into exo. EDIT: It would probably be best to work on these simultaneously, to not create any blocking. Staapl for pure nostalgia, DIP, 5V, and the Blue pills for ease of programming in Rust, C. Entry: A/D envelopes Date: Fri May 8 15:38:04 EDT 2020 Is it actually difficult to create envelopes? Suppose it is straightforward to create oscillators, what would be needed to do gating? I'm only interested in percussive sounds. Entry: PWM EIDAC Date: Fri May 8 15:42:13 EDT 2020 Would this work with PWM? It would have to switch between ref and ground. Actually no. It would just need to switch between ground and open, tolerating analog voltage. Actually the base voltage is going to be quite low. Digital input will be ok with that. Let's assume this can be driven fast enough from a simple uC interrupt routine such that the ripple isn't too much. With a single CA3046 I can do: 1 reference 2 emitter cooupled pair 1 oscillator + frequency feedback 1 amplifier Add to this a capacitor switcher bank to trade off between attack and precision. Here's a thing: a signma-delta converter has high frequency in its mid range. Can I just stick to the mid range? E.g between 1/3 an 2/3 there the cycles are 001 an 011. Between 1/4 and 3/4 it is 0001 and 0111. Schem: [ref_base]-|>--[10k]--X--|>-[drive_base] | [22k] | uC OC Pin -C | GND This could just be a first order S/D that updates at say 10x audio sample frequency 0.5MHz Probably less is also ok. This is not too hard to get going as long as the outputs can switch fast enough. What is needed? - S/D code test in assembler - VCA driven by sink current. Maybe the EC pair? - filter Entry: Optimized TB Date: Fri May 8 16:37:30 EDT 2020 Suppose my input is digital. Is there a circuit that looks like a ladder filter but is just digital? It should be possible then to use the EIDAC to create a square-wave signal by turning it on and off. Different topology: - 1x ref - 2x filter - 1x gain + modulation (gain square) Entry: Practical? Date: Fri May 8 17:00:14 EDT 2020 I know the EIDAC works, the PWM or S/D is probably also going to work. The main unknown is the filter. So maybe build it on a separate breadboard? I can wire up a bias network for a CA3046 to be able to manually set the current, so I can get the ladder set up. I can use the existing circuit for that. The PIC code should still be ok. Entry: Breadboard Date: Fri May 8 18:57:13 EDT 2020 IIRC there was some code to at least set up the spi port. I can't find it though. Probably saw.f Indeed, that references mcp4922-init-spi and mcp4922-tx-A, B I had to flash the board again. On zoe: cd /i/exo/staapl/app make dip40kit.flash /usr/local/racket-6.1.1/bin/racket dip40kit.dict /dev/ttyACM4 load saw.f init-saw 255 A 10 A Saw shows clearly on the display. This is enough to just do the analog bits. Entry: PIC vs. ARM Date: Fri May 8 19:02:53 EDT 2020 Still on the fence about what to really do with this. It is hard to build anything complicated with it, compared to being able to run code in a test framework. This is entirely made of nostalgia.. But let's just put a blue pill on that board. At least that way the decision can be made easier. EDIT: Yeah I keep going through this loop: I keep tinking that this is just insane to work like this, and then I get a spark to try something and I am filled with joy. Maybe just keep it around. Can I mount this so it hangs? Entry: Debugging filter Date: Fri May 8 21:31:10 EDT 2020 There was something wrong: some virtual ground was not connected correctly. Now without resonance I can see the filter have effect when I set DAC B. It does still "thump" a bit when switching. I've set the saw series resistor to 100K. It is giving resonance, but the resonant output is of course the _input_ of the ladder network, not what can be measured at the output of the diff amp, because that has been low-pass filtered again. With resonance up it behaves as high pass. I will need to debug this thing a bit more. It's doing something right, but not exactly what. Entry: VCA Date: Fri May 8 22:41:43 EDT 2020 So next missing piece is VCA. I have one transistor left in the CA4036. I guess it's not that hard. Common emitter? Gain is g_m R_c Couple AC signal into the base voltage? Yeah just use another opamp for that. I think it's time to switch this over to something actual. Let's try to get a S/D signal out of an STM32F0. JLCPCB - LM324 $0.0767 - STM32F030 TSSOP-20 $0.5838 Entry: PWM Date: Sat May 9 10:17:46 EDT 2020 What about PWM? On a Blue pill at 72MHz, 16 bit PWM will end up at (/ 72.0 (* 64 1024)) 1.09kHz That frequency is way too low. PDM is going to be much better. Let's just try this out. What about a combination? PDM with guaranteed dominant period? It's probably enough to just keep it in a certain range, e.g. 1/4 to 3/4. Design parameters? Say we stay withing the mid range setting sominant period to 4. This requres only 200kHz which isn't all that bad. EDIT: Putting it that way, it shouldn't be too hard to compute the spectrum analytically for this. Entry: sm32g4 board Date: Sat May 9 21:58:41 EDT 2020 https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/b-g474e-dpow1.html https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-g474re.html https://www.digikey.com/products/en?keywords=NUCLEO-G474RE Entry: Transistor Date: Sun May 10 19:20:49 EDT 2020 BCM847 $0.1420 - countour frezen - common base thick trace MPQ6700 2x pnp 2x npn Entry: Thump Date: Mon May 11 08:53:40 EDT 2020 When frequency changes, a thump can be heard. This is likely due to there not being any gradual transition. In typical circuits, the signals comes from an envelope that is not just a step. Should go away once there are gradual slopes. Entry: PDM Date: Mon May 11 12:22:42 EDT 2020 Basic skeleton of PDM is up. Resolution is 32bit just because it doesn't cost anything extra. Next is to connect it to GPIOs. EDIT: Ok got it to work using the BSRR register. There is a couple of percent of jitter, but that shouldn't matter once the signal is properly filtered. Next is to make it open collector. This requires just setting the output control, so it is actually much simpler. Maybe test it with pull-up enabled? Entry: analog/doc/current_ref_multiplied.jpg Date: Mon May 11 14:53:56 EDT 2020 Same idea as previous regulator, but instead of regulating the base directly, do it through a voltage divider. This should give a scaling of the base voltage. One modification: add another buffer between the divider and the base. Entry: Modulation filter Date: Mon May 11 15:01:40 EDT 2020 It needs to do a couple of things: - switch between say 4/3 ref and 1/3 ref. - add a time constant let's set it up as a second order filter and then see how it can be modified. https://www.electronics-tutorials.ws/filter/second-order-filters.html That one makes it easy to add gain, so the main question is how to switch between the two regimes? The problem is that impedance changes in the old circuit, which requires a buffer. Stuck on the input impedance change. I can't find any second order filters that have infinite input impedance and zero output impedance. First order I can come up with this: analog/doc/inverting_first_order.jpg Actually there is no current flowing from Vref to the (-) input so that resistor can be removed. Yeah that one doesn't work as I think it does. With mosfet pulling down, the voltage is higher than (+). But it does give the solution in that it clearly shows how to look at the circuit: 1. The mosfet decides whether to inject constant current into the virtual ground or not. 2. We can put the virtual gorund wherever we want This can probably be generalized to a different order filter. Entry: Parameters & requirements Date: Mon May 11 16:12:06 EDT 2020 1. Reference current is max current => Vmax 2. Min current corresponds to 3/4 Vmax. It seems that 2/3 Vmax is too large of a span. But this can be revisited later. 3. Splitting the PDM range into regions 0,1,2,3, we will not use regions 0 and 3 because their modulation periods are too low, so the levels become: % Vmax - 0 62.5 not used - 1 75 ------------ - 2 useful range - 3 100 ------------ - 4 112.5 not used 4. Doing it this way means that care should be taken to never regulate the transistor into the high current unused range. So let's take a moment to think about safety. There are essentially two regimes that need to be safe: - Circuit startup, when mosfet is open circuit. At this point we would be driving 62.5 Vmax which is ok. - Modulator regime. As long as there is no bug in the code that causes the output to short to ground and case a constant 112.5% regime, it is probably possible to ensure that the converter is never programmed outside of the useful range. 5. Using an inverting scheme, the refernce point should be at 62.5% Vmax when the mosfet is not engaged, and 112.5% Vmax when it is engaged. 6. Dividers: 62.5% approx (/ 2.2 (+ 1 2.2)) 0.6875 112.5% - 62.5% = 50%, which is what needs to be added to the 62.5% offset. This is 125% to 50% or 12 to 10. It's probably ok to stay in the E3 series, so use 10k/10k Then do an order of magnitude. Say keep pole at around 1kHz 7. The current set point. I forgot. Let's just pin the collector at half of 3v3. (/ 1.65V 2.2k) 0.74mA That's probably ok. 8. The polarity of the reference is wrong? Because the transistor is inverting, the feedback needs to go to (+) side of opamp. EDIT: I can't get this to work without oscillation. I'm side-stepping the issue and will just use one of the transistors in diode configuration with a current set resistor to 3v3 + a buffer for the Vbase. See paper notes. 9. What is a good value for the lowpass? Resistor is 100kOhm 100nF 10ms 10nF 1ms Entry: Second breadboard Date: Mon May 11 18:34:46 EDT 2020 - STM32F103 blue pill - Voltage reference - PDM EIDAC - Saw + ST I'm thinking th saw can still be added later. In a first iteration it seems much more interesting to start with a digitally controlled oscillator, and an analog VCA and VCF. To make the saw work, an extra interrupt needs to be added. Or the saw state can be checked in the 200kHz loop. There are plenty of avenues from there. But otoh the saw is a really simple circuit to test if the EIDAC works properly. Here's a roadmap: 1. Set up the 0.6V reference with a CA3046 2. Create PDM 3. Sawtooth with ST EDIT: So I have het PDM->frac vref +- working, but I definitely need to get a better feel for not messing up the feedforward transistor. It would probably be best to add some clipping. Entry: PDM asymmetry Date: Mon May 11 23:17:44 EDT 2020 Something is not the way I imagine it: set V 0x4 -> 0.88 0,08 0x8 -> 0,80 0,16 0xC - > 0,64 0,20 open -> 0,48 The time constant is a-symmetric. - when transistor is off, C discharges through parallel resistor only. there is no current to the virtual ground, so also no current on the other side. - when the transistor is on, the current starts flowing to ground set by the resistor that is swithced in, but not all current goes through the cap. So what to do about that? Construct the PDM signal between 0V and Vref by pulling it to ground through a resistor, then buffer that signal and send it into a filter. I guess it is necessary to use two opamps. One to provide high input impedance, and one to provide low output impedance. I guess it's just not possible to filter while doing both. The original circuit also had a buffer, just that one was in the DAC. Entry: Use two opamps Date: Tue May 12 00:15:28 EDT 2020 That way there are many ways to solve the problem. The main thing seems to be to add or subtract, and to do it symmetric or one sided. Let's focus on a symmetrical approach: - Useful range between 70% and 100% Vref - Midpoint at 85%, +- 15% - Full scale is double of that 85% +- 30%, or 115% - 65% Found something: 1. PDM is pulldown from shared reference A 2. Low pass midpoint also shared, B This gives max sharing, minumum components. So what should the setpoints be? The output then goes between: B - (A - B) = 2B - A B + B = 2B So core idea is that if mosfet pulls down, the low pass filter's output will be double its midpoint. Let's fill in some things: Two reference voltages: A = 10 to 10 divider 0.5 B = 10 to 22 divider (/ 22.0 (+ 10 22)) 0.6875 2B top range: (* 2 0.6875) 1.375 Closed: (* 2 0.6875) 1.375 75%: (- 1.375 (/ 1.0 8)) 1.25 50%: (- 1.375 (/ 2.0 8)) 1.125 25%: (- 1.375 (/ 3.0 8)) 1.0 Open: (- 1.375 (/ 4.0 8)) 0.875 ( - 1.375 0.875) 0.5 sweep The useful range is then between 1.25 and 1.0 Why are these numbers so round? EDIT: There's a simple idea here. So this is just a see-saw.. What about using only 1/2 and 1? This way it is still possible to use the edges of the modulation range to do things, and it will be safe, but the useful parts will be in the mid range. With both ref points at 50% Vref, mod frac mV ------------------------------ 0000 -> 8/8 (shorted) 700 0001 -> 7/8 high 612 0101 -> 6/8 mid 525 0111 -> 5/8 low 437 1111 -> 4/8 (open) 350 Then do something else I forgot about: use one of the channels to set the overall reference voltage once it is figured out why the circuit oscillates. Roughly we have 20mV per octave With full scale regulated to 700mV we have almost 9 octaves in the optimal range. I think that's probably enough. In analog/doc/buffer_seesaw.jpg A=B=Vref/2 R1=R2 R3 irrelevant. EDIT: Not really. I had it at 220k but moved it to 10k because it otherwise didn't transition fast enough. Then later this can be translated to 2nd order sallen-key filter. EDIT: Measurements using: pdm ! {setpoint, 0, F}. F mV --------- 1.00 357 0.70 480 0.50 580 0.25 692 0.00 698 Not really linear, but I guess it is good enough. EDIT: Seems to be op amp slew rate. Might be good to instead use a transistor to modulate the digital signal onto Vref/2. Let's move on. To summarize: opamp usage: - Vref buffer - Vref/2 buffer - PDM Vref/2 modulated buffer - Low pass filter (seesaw) Entry: MFB filter Date: Tue May 12 08:52:10 EDT 2020 Advantages over Sallen-Key https://www.ti.com/lit/an/sboa114/sboa114.pdf Entry: Schmitt trigger + Saw Date: Tue May 12 09:20:50 EDT 2020 Needs two amps: one to buffer the integrator, one for the schmitt trigger. Let's start with what is needed to discharge the cap. The original circuit had a PNP to do this, which discharges when the ST has output low. Can I do it directly? E.g let the S/T go high when the signal goes low? Entry: slow opamp Date: Tue May 12 11:38:15 EDT 2020 The root of the problem is that I want to avoid a multiplication by Vref, so I derive it by modulating it using a pulldown and a buffer. Problem there is that the opamp can't deal with those fast edges. So either use another type of buffer, or avoid the problem entirely by introducing some kind of multiplication into the system, e.g. either digitally by incorporating the gain in the PDM signal and relying on excess range for trimming, or some other means. Entry: Feedforward only Date: Tue May 12 11:47:59 EDT 2020 I'd like to keep it simple first, so the idea is this: - Create the 0.7V signal from 3v3. - Measure one of the transistors with an ADC to create a fairly direct temperature measurement that can be used to compensate. - Or always measure the frequency of one of the oscillators to find the compensation factor. The latter frees up a transistor, but exposes risk, unless a resistor is added to limit the current. That resistor would introduce nonlinearity but that's probably better than risking to blow up a transistor. The LM324's output swing is V+ - 1.5V So let's assume this is 3.5V Max current for CA3046 is It specifies max collector current at 50mA. Typical beta is 100, so 0.5mA Between 3.5V and 0.7V is say 3V drop, so that (/ 3 0.5) -> 6k base resistor Let's give it a try with 10k? (/ 0.7 3.3) (/ 22.0 1.22) So that's about 22 over 122 Maybe let that be the 75% range? So (* 0.75 3.3) 2.5V (/ 0.7 2.47) 0.28 (/ 1.0 (+ 1.0 2.2)) 0.31 So: Divider: 10k / 22k Current limit: 10k Entry: Schmitt Trigger cont Date: Tue May 12 12:30:17 EDT 2020 I need to make sure I understand the circuit. Ok got it. See "Schmitt trigger implemend by an inverting comparator." https://en.wikipedia.org/wiki/Schmitt_trigger Referenced to 3v3 / 2 instead of ground, and using two equal resistors. Saw + pulse work. There is going to be some work needed for tuning component values. Probably next step should be frequency measurement. EDIT: exti was simple to do. dht11.c had code. Next is period measurement, which is easiest to do with the ARM 32 bit cycle counter CCNT. It's on F4, also on F1? 0xE0001004 DWT_CYCCNT EDIT: Yes this works The regulation should be straightforward once there is a control loop. Moving on to the next item: component tuning. Entry: Components and ranges Date: Tue May 12 15:34:01 EDT 2020 Maybe first put a knob on it to make it a bit easier to control? Also needs a balanced output. Entry: balanced output Date: Tue May 12 15:44:55 EDT 2020 The point here is not necessarily to put out a complementary signal, but to create two lines with the same impedance. One could just be the reference signal. Put the "silent" line on the ring, such that that one shorts when an unbalanced cable is plugged in. According to wikipedia: "A typical line out connection has an output impedance from 100 to 600 Ohm." I'll use 510. https://en.wikipedia.org/wiki/Line_level Entry: Hex inverter Date: Tue May 12 21:32:09 EDT 2020 Using 74HC14 Schmitt trigger hex inverter to clean up the PDM that comes out of the uc, which is very noisy. JLCPCB 74HC14D, 74HC04D $0.10 (basic) Entry: Fixed EXTI priority Date: Tue May 12 21:33:17 EDT 2020 This caused issues. Now we have: pdm: info: TIM5 pri 0 pdm: info: EXTI0 pri 16 (/ 72000000000 6977164) Entry: Next? Date: Tue May 12 21:47:44 EDT 2020 - Digital regulator - VCA - VCF Entry: MIDI TRS Date: Tue May 12 21:52:08 EDT 2020 http://www.interfacebus.com/PC_MIDI_Pinout.html https://www.midi.org/articles-old/trs-specification-adopted-and-released Entry: VCA Date: Tue May 12 23:45:07 EDT 2020 Matched pair + drive. That's most of a CA3046 I have a bunch of them now, so why not. The LM13700 and CA3080 take a sink current. Though they might be driven like a transistor also. CA3080 has a raw junction input, so might work like that. LM13700 has a different layout. So here the path diverges. If I want to prepare for using discrete transistors, I should not use the OTAs. Use the CA3080 instead. Wait a minute. Can I use a diode as amplifier? Here's a CA3046 VCA: http://hem.bredband.net/bersyn/VCA/ca3046%20vca.htm And here's a simpler one with opamp diff amp stage: https://1.bp.blogspot.com/-R2OviyS-FDo/VhvRC9lfGDI/AAAAAAAACGk/0Zdv9lX2vr0/s1600/YuVCASimplified.png Entry: Diode VCA Date: Wed May 13 00:27:36 EDT 2020 bottom sets current. small signal mixed in Entry: Final architecture Date: Sat May 16 14:10:11 EDT 2020 Maybe best to first build a couple of prototypes with what I have here. Meaning manually assembled or breadboarded, using CA3046 chips. A single voice would then need two of those: - each chip a sawtooth oscillator with optional polarity reversal so it can also do pwm. the oscillator is then the temperature compensator. - VCA: matched pair + setpoint (1 left) - VCF: matched pair for setpoint (2 left) This can go on the current breadboard. I only need one instance to then finish the firmware for it. Entry: Frequency estimator Date: Sat May 16 22:37:56 EDT 2020 Here's an interesting issue. Is it ok to update frequency estimate filtering at the zero crossing point? E.g. when using a 1-pole, this essentially shifts the filter's pole in tandem with the measured frequency. This seems reasonable. Entry: Distortion plug board Date: Sun May 17 16:41:46 EDT 2020 Use the "framework" approach for building distortion pedals. Basically, pre and post EQ I have that covered. Just put a clipper in there with pluggable diodes etc. Entry: MIDI Date: Sun May 17 17:46:33 EDT 2020 Might make most sense to create a standard interface next so this thing becomes playable. Do it in a couple of steps: - SLIP-encapsulated MIDI stream or midi-like events - hardware uart - USB Entry: Hooks for pots Date: Sun May 17 18:03:33 EDT 2020 Small hooks can be used to mount pots on wood boards for prototyping. Entry: Frequency feedback Date: Sun May 17 18:58:18 EDT 2020 Probably best to take the frequency estimate and map it back to CV scale by taking logarithm before doing any regulation. Entry: Analog switch chips Date: Sun May 17 20:42:33 EDT 2020 I have a bunch of these. In fact I have so much stuff here I have years to exhaust it all. So what I really need to do is to remove impediments and start putting things together. One big impediment is breadboarding. I need a different style. Maybe time to start dead-bug? What I need first is glue. Entry: Fuzz vs. Distortion Date: Sun May 17 21:27:57 EDT 2020 In an op-amp circuit, the difference is mostly in where the diodes are. There are essentially two placement points: - In the feedback loop: this combines two log curves to give soft clipping. The gain resistor is in parallel, so if this is left out, the gain is "infinite", giving a fuzz. - Buffered, through a resistor into two diodes that clip to ground. When the signal is low, diodes do not conduct, when signal gets high, diodes will start to conduct and clip. Entry: LM324 crossover distortion Date: Sun May 17 22:17:56 EDT 2020 I ran into some posts from 2011 mentioning crossover distortion can be limited by biasing the output into class-A operation, either down or up. Biasing downward might be better because it can sink more current. This might be one of the reasons why I had issues with the filter. Entry: Offset fuzz Date: Tue May 19 00:58:09 EDT 2020 Very high gain square wave fuzz + offset. Should have a gating effect. Entry: Bazz Fuss Date: Tue May 19 01:25:07 EDT 2020 http://www.home-wrecker.com/bazz.html Entry: cmos fuzz Date: Tue May 19 01:32:05 EDT 2020 https://www.parasitstudio.se/building-blog/cmos-workshop-part-2-square-wave-fuzz Entry: input buffer Date: Wed May 20 23:30:22 EDT 2020 Here's an example: https://www.diystompboxes.com/smfforum/index.php?topic=95026.0 Input impedance of that one is probably way too high. Entry: Typical balanced signal? Date: Wed Jun 3 18:56:22 EDT 2020 I'll need an inverter anyway, so it might be interesting to generate a balanced signal by passing it through another time and avoiding the CAP that way. There are two standards: +4 and -10 https://en.wikipedia.org/wiki/Line_level The most common nominal level for professional equipment is +4 dBu. For consumer equipment it is −10 dBV. +4 dBu is 3.472 peak-to-peak. So if 1.7V common mode is ok, that is all that is needed. Let's put a pwm output on the PDM board as a main digital oscillator. Entry: PWM Date: Wed Jun 3 20:43:52 EDT 2020 Enabled PWM on the timer that drives the PDM interrupt. It's pretty much free, so let's use it for some digital sounds. Entry: Hard sync Date: Wed Jun 3 20:45:29 EDT 2020 Is a nice thing to have. Requires an or gate. But since it is single ended, can just be a resistor and a switch. EDIT: This is turning into a project! I don't really need a saw tooth to do hard sync. I've hard-synced the PWM wavetable synth, which can do all kinds of overtones while still sounding "filtery" and synced to the analog. Let's check interrupt jitter as well: it's about 2 uS, and seems fairly random. Entry: 74HC14 as Schmitt trigger for oscillator Date: Thu Jun 4 00:05:26 EDT 2020 That seems to work, but the opamp buffer from sawtooth cap into inverter now cannot also handle the audio output, so I put another buffer there for now. Entry: Summary of today's work Date: Thu Jun 4 00:14:57 EDT 2020 1. pwm output enabled, 9 bit resolution / 140kHz 2. sub osc driven from input 3. hard sync for pwm output 4. use 74HC14 as Schmitt trigger for sawtooth seems better than opamp 5. add some buffering: cap charge buffer should only drive the schmitt trigger, not extra audio output, and schmit trigger discharge output should only drive the discharge diode, not any other pulse outputs. 6. i had to bias the 1/2 3v3 reference buffer output with 1k to ground to make it class A, otherwise it would oscillate. 7. cleaning up the pwm output with 10k / 10n + also bias 1k to ground for class A. 8. some issues with exti. sometimes it just overruns and i do not understand why. probably interference with pwm. it might be possible to handle exit inside the pwm isr? sub osc is going to be bass anyway so a bit less resolution might not be a problem. Entry: PWM output Date: Thu Jun 4 01:00:38 EDT 2020 It is of course possible to digitally pre-emphasize the output to compensate for slow rollof of output filter. Entry: Power supply filter Date: Thu Jun 4 03:32:57 EDT 2020 Johannes says put a resistor in there. Trying this and it is better: 100uF / 22Ohm Also disabled the LED because that modulation was still showing up in the PWM output. Entry: Discharge Date: Thu Jun 4 10:37:00 EDT 2020 Maybe it's just not a good idea to tie that discharge diode to the inverter directly? EDIT: Buffered it again to get some sharper edges. That seems to work better. Entry: More about the wavetables Date: Sat Jun 6 01:23:24 EDT 2020 So let's make hard-sync the default. Generate the waveform parameterically, which will get rid of the chipmunk effect and will behave more like an impulse response synthesizer. I think there is something interesting hidden here. Entry: Practical: next? Date: Sat Jun 6 02:18:39 EDT 2020 Expose all parameters and make a small ui for it together with a "range tuner". Actually, why not make a gui for that? Entry: Lock step control update Date: Sun Jun 7 01:23:35 EDT 2020 I want to run PDM/PWM in linear interpolation mode with a lock-step power of two control loop. Is it enough to do this in the main loop instead of interrupt? Is there any lower priority stuff? Maybe software interrupt? https://community.st.com/s/question/0D50X00009XkYGlSAN/software-interrupt-nvic EXTI_SWIER Entry: roadmap Date: Sun Jun 7 17:05:35 EDT 2020 exti user interrupt -> compute log in control handler + update -> add midi then maybe create a small envelope? I can compute the log in the main handler. That's not a problem. Entry: Top side current sources Date: Mon Jun 8 02:43:54 EDT 2020 Now that the DAC ground reference requirement is gone, why not use top side transistors? This would work for driving OTAs. For the currenct circuit it really doesn't matter if it's PNP or NPN. This has one: https://www.birthofasynth.com/Thomas_Henry/Pages/VCA-1.html EDIT: The basing there works because there is plenty of room between 0V and the -15V which is what the CA3080 set current diode is referenced against. I can't do that particular trick in my setup. Probably also 5V is not enough for the CA3080. Time to start a Eurorack-referenced +-12V design. It's cute to try to do this on 5V but really quite a pain to build anything complicated. Entry: Just the CV converter Date: Mon Jun 8 11:08:03 EDT 2020 So if I focus on just making a CV converter, and stay true to Eurorack levels, what would be necessary? Power: +- 12V Audio: +- 5V Control: +- 2.5V bipolar, 0-8V unipolar (1V/Octave) Digital: +- 5V Entry: The control system Date: Mon Jun 8 23:16:24 EDT 2020 I think this is the first practical control system that I've built. Compared to i/o filtering, this is different. c += g e e = o_s - o_m Where: c control input g error gain e error signal o_s output setpoint o_m output measurement EDIT: ok the basic feedback mechanism works, but the aliasing in the measurement and the control signals leads to oscillation. So I'm going to have to add some compensation there. EDIT: Still doesn't work. But those broken control algorithms are actually quite interesting :) Let's commit current state 9a9e26f29ac65fc766b487445fa4e456d6d1d816 broken pitch control algorithms sound interesting So how to fix? Moving average? Entry: The measurment Date: Tue Jun 9 00:23:44 EDT 2020 So that was a visceral experience! Of course the control system is only as good as the measurement, so the measurement needs to be cleaned up first. Measuring wave time stamps is problematic. The aliasing is an issue. Looks like I have the control system backwards. 1. There are many delays and nonlinearities in the system that interfere with analysing this as a simple feedback system. 2. What I really want to do is to temperature compensation, which is a slow update procedure starting from initial calibration, and then evolve the model over time only very slightly, compensating for temperature. So let's start with a calibration procedure that is based on a much more precise measurement. Basically, as long as the setpoint is constant, we can make a note measurement. That should be the base calibration routine mapping set point to actual frequency. That can then be tabulated and turned into a polynomial. EDIT: I have a precise frequency measurement. Entry: Calibration Date: Tue Jun 9 00:34:14 EDT 2020 I'm removing the control and filter algorithms, because they do not solve the right problem. For reference they are pasted here. Last git was: 9a9e26f29ac65fc766b487445fa4e456d6d1d816 broken pitch control algorithms sound interesting A. MEASUREMENT SMOOTHING #if 0 /* This I find very hard to think about, because if the control side isn't stable, then this doesn't help either. */ /* New measurement is the elapsed time since last capture. */ int32_t measurement = cc - last_cc; /* We filter that using a first order filter. Note that this is updated at the oscillator's current rate, so the filter time constant in real time depends on the frequency of the oscillator. */ int32_t estimate = osc_period; int32_t coef = (osc_mfilter.uint32 >> 1); int32_t diff = measurement - estimate; int32_t update = (I64(coef) * I64(diff)) >> 31; estimate += update; /* Save state */ osc_period = estimate; #endif #if 0 int32_t measurement = cc - last_cc; /* Moving average. Store accumulator and sum in a single uin32_t so we can use atomic updates based on word read/write. */ uint32_t ma = moving_average; uint32_t count = ma & 0xFF; uint32_t sum = ma >> 8; if (count < 0xFF) { sum += measurement; count++; moving_average = count | (sum << 8); } #endif B. CONTROL ALGORITHM /* 5.27 negative fixed point base 2 log. */ // FIXME: 1. double buffer the pdm setpoint, 2. do linear // interpolation of the actual set point. /* We regulate the log_period to the setpoint using a linear integrating regulator. The basic first order integrating control algorithm is: c += g e e = s - m Where: c control input (channel[0].setpoint) g loop gain (osc_glide) e error signal (error) s setpoint (osc_setpoint) m output measurement (osc_measurement) The measurement and setpoint ar in 5.27 negative fixed point base 2 log. The log operation ensures that the relationship between the control and measurement is roughly linear. Any remaining non-linearity can be handled by the feedback. There are a couple of inversions in the control and feedback chain: - setpoint: inc - 74HC14 inverting buffer: dec - saw frequency: dec - saw period: inc - perod nlog2: dec So from setpoint to nlog2 we have an inversion. Expressing the algorithm in standard form where the measurement has a minus sign, we need to add another minus sign in the loop to compensate for the extra inversion, e.g. "-=" The control pole is in 0.32 form, but we perform 1.31 signed arithmetic because the error is signed, so it is shifted by one. */ uint32_t osc_measurement = nlog2(osc_period); int32_t e = osc_setpoint.uint32 - osc_measurement; int32_t g = osc_glide.uint32 >> 1; int32_t g_e = (I64(g) * I64(e)) >> 31; channel[0].setpoint -= g_e; Entry: Calibration Date: Tue Jun 9 01:48:15 EDT 2020 This requires some sequencing. Should it be implemented as a loop on the controller? Or should I do it in Erlang? Here's an algorithm for the controller. Start at mid range, then go up to 20 khz and down to 20 hz. Mid range shoud be (* 20 (sqrt 1000)) 632.4555320336758 Which is between Eb5 and E5 https://www.liutaiomottola.com/formulae/freqtab.htm It's much lower in the circuit with 22nF. I estimate about 8Hz. Replaced it with a 2nF and now it seems more stable. I can't believe that is just the cap. Maybe there is something to learn here: map the midpoint of the PDM onto a high frequency, as that has the least amount of modulation? Now useful range is 0.37 to 0.55. I'm actually quite interested in getting at that curve. What about: - Start at 0.5, go up until past 20kHz - Start at 0.5, go down until past 20Hz Let's add an RPC mechanism and do the exploration form Erlang. Too much work to do this on the controller without blocking tasks. 1. set meas time, osc freq 2. throw away two measurements 3. repeat Entry: synth control midi Date: Sat Jun 13 15:35:10 EDT 2020 It's integrated as exo epid. Next is to play with parameter mapping, and probably also make the blockingrpc mechanism work. EDIT: Measure RPC works. Also cleaned up things a bit, useful for future. Entry: Custom algorithm. Date: Sat Jun 13 21:57:49 EDT 2020 Every time you play a note, measure it. Then use some kind of update algorithm to update the table. Initially it is probably best to tune in the usual sense: pick a note, and perform a couple of linear interpolating root finding steps. Do one per octave. Then interpolate linearly in between. This seems much more direct. Entry: Interference Date: Sun Jun 14 10:15:41 EDT 2020 Some frequencies sound much rougher than others. I wonder if this has to do with the modulation pattern lining up with the wave somehow. Is there anything that can be done about it? - 2nd order filtering - adding modulation or noise When such a rough frequency is found, it would be interesting to see how sensitive it is to changes in setpoint. Also: there is probably some influence over periodicity by setting the lowest bits to zero. Entry: Vactrol Date: Mon Jun 15 01:48:12 EDT 2020 Create vactrol with green LED and GL5537. The vactrol has 30ms response time, so can probably be used as a smoother as well. One problem is that it is not an exp conv, but that can be solved by putting a transistor in front. Entry: Review Date: Tue Jun 16 13:39:53 EDT 2020 So what do I want to do with this? A number of things still need to happen. VCA is probably the most important one. VCF can wait as I have Johannes' circuit. Sticking to 5V is probably not a good idea, so there is a bifurcation: 5V: hacky cheap synth +-12V: eurorack multi-cv Let's not aim for anything commercial yet. In the first place this has to remain fun, and also simple so I can build a circuit. Let's focus on the calibration and CV modulation artefacts first. Entry: Root finding Date: Wed Jun 17 11:59:17 EDT 2020 Made basic rootfinding step for pdm calibration. Next is to make a plot for the non-linearity of the transfer function. Entry: Rust Date: Thu Jun 18 17:23:39 EDT 2020 Time to move into rust. Keep the scaffolding in Erlang for the moment, but start offloading some tasks to Rust state machines or async tasks. Then it should be perfectly possible to move things around. Entry: Dumb stuff Date: Thu Jun 18 18:05:06 EDT 2020 Maybe wire up the filter? I'm actually quite curious now how it behaves. A filter can act as a makeshift vca also. Entry: Calibration Date: Thu Jun 18 18:06:06 EDT 2020 What variables are there? - Temperature - Voltage - Component drift The latter is probably not so important. Temperature is quite important. Voltage is probably fairly stable, but the circuit is very sensitive to that. There is likely going to be some temperature variation here. So bottom line is that I probably need a continuous pitch measurement, and feed that into a slow pace calibration routine. Whenever the pitch is kept constant, the measurement can be considered stable. How to sequence that? Entry: Good pitch measurement Date: Thu Jun 18 18:14:28 EDT 2020 What about this: create a 2-way pipe betwen the modulation setter and the pitch measurement. Basically, whenever the modulator changes frequency or goes into glissando mode, the measurement needs to be disabled. The first and last period need to be removed from the measurement. The current set point needs to be sent to the measurement so it can be later added in the annotation. EDIT: This can go into a separate module. 1. Accept new setpoint 2. Throw away last measurement and send stata onward if it is accurate enough 3. Createa a new state, throwing away first (couple? of measurements). This will produce a steady stream of (setpoint,measurement) pairs that can be used to feed into the model update algorithm. Entry: Loops Date: Thu Jun 18 19:32:26 EDT 2020 It was a good idea to create a small loop synth. It sounds much more alive like this. Two things that are missing: glides and temp comp, because the latter is significant. Where to compute glides? Ok to do this in PDM interrupt? Entry: How many pulse width modulators are there on the f103? Date: Thu Jun 18 19:43:50 EDT 2020 It has 4 compare registers per timer. Maybe that is actually much better. Use PDM modulated PWM? How to control the last bit? Send out the integer part via PWM, then send the fractional part into a PDM, and add an extra cycle when it overflows. Same principle. I think I want to try this out on a different board. Currently I really don't need more than 4 controls. For TIM3, the outputs are: 1 PA6 2 PA7 3 PB0 3 PB1 Entry: Impulse synthesis Date: Thu Jun 18 19:47:06 EDT 2020 Instead of wave playback, this 250kHz PWM resync can also be used to do modal synthesis. I.e. a pulse that excites a number of damped exponentials. This can be combined with the PDM scheme above to create more precision. So I catually don't really need an analog filter yet :) - It would be a filter, essentially, so there is no resampling aliasing. - Because period has a lot of jitter, any aliasing due to the pulse alignment woult get spread out. Entry: Damped exponential Date: Thu Jun 18 21:27:41 EDT 2020 So what is the update equation? Resembles a physics sim update. What's it called again? Symplectic integrator. https://en.wikipedia.org/wiki/Symplectic_integrator With energy loss, a basic form has 4 multiplications. p+ <- b p + a q q+ <- b q - a p+ Maybe it's possible to let it loose energy only at one end? p+ <- b p + a q q+ <- q - a p+ Yes of course that is possible. Question is if it is a good idea. The a coefficient is going to be small enough to fit the <0.5 fixed mul high word constraint, but b will be around 1. in the 0.5 range of a high word fixed point mul. Maybe best to rewrite it as: p+ <- p - b p + a q q+ <- q - b p+ - a q+ Where b is small as well. Then remove the energy loss term at one end: p+ <- p - b p + a q q+ <- q - a p+ The rotation/mixing is necssary, so can't get rid of that one probably. So what is this called? A lopsided svf? p += (U64(a) * U64(q)) >> 32; p -= (U64(b) * U64(p)) >> 32; q -= (U64(a) * U64(p)) >> 32; Now what is left is to set the hight of the pulse to be injected