[<<][synth][>>][..]
Sat May 17 18:30:59 EDT 2014

ISR: one or two comparators?

Discharge pulse takes too long: 60 cycles.  

So this either needs 2 comparators (like a 555) or a timer interrupt
to stop the discharge.

How to dispatch on the comparator interrupt?  One of the phases is not
needed.  How to ignore it fast?  State is from: CMCON<7:6>, so that's
BTS, RETFIE.

Let's see... If the discharge transistor is activated as the first
instruction in the ISR, it's probably going to pull the voltage below
the comparator's threshold pretty quickly, so every time it goes over
just be stupid and initiate a discharge sequence:

- LAT <- 1
- TMR <- delay
- clear IF

If then due to noise this gets called multiple times, it's not an
issue: it will just reset the timer.  Timer ISR is:

- LAT <- 0
- clear IF

This looks pretty simple.  Both interrupts need to be multiplexed in
software, probably best to check the comparator one first.

if CMIF
if TMRIF


Actually, turning the pulse off can be done using the output compare
module.




[Reply][About]
[<<][synth][>>][..]