Sat May 17 11:46:49 EDT 2014
Looking for a good ISR structure on PIC 18F4550
Problem is that there are two high priority interrupts. The low
priority one (USB) should be easy to handle correctly.
The fun part here is that it is quite time critical, so probably
requires some instruction tweaking.
- DAC SPI out (timer?)
It's ok to add a little delay to the DAC SPI out. However it would be
great to do any comparator magic in HW.
First need to look at how the comparator works, and how it combines
To use the comparators to create a sawtooth wave charging a capacitor
with a constant current. Some remarks:
- Set up to monitor voltage over capacitor compared to 2/3 V_DD /
V_REF+ via internal voltage ref. There are 16 steps here which
gives some amplitude control.
- On interrupt: question is if comparator output can be used to
discharge the cap. That would give best performance, but without
hysteresis is quite unpredictable.
An analog time delay on the input is maybe enough.
- Integration cap probably needs to be buffered before going into
comparator input. DS mentions R_S < 10k. There's 0.5uA leaking
current which definitely puts it near the desired range (10mA -
10uA). Note this is also a problem for any opamp follower (LM324N
- Picking a scale: what about keeping it simple and map uA to HZ?
This as 20mA at 20kHz. It does mean that discharge currents at high
frequency become quite large.
- Picking a discharge method: is a NPN transistor good enough? Should
it be a FET? Can it be a PIC pin? Probably not a good idea since
it's a surge current.
- Add histeresis with an external resistor network. This allows the
interrupts to be used just for timing, but control remains in
hardware. Base this on the reference voltage if possible.