Thu Jan 6 11:19:38 EST 2011
Compensated Sawtooth Oscillator
Moving forward from . The absolute bare-bones circuit for a
sawtooth oscollator with exponential current drive is something like
TRIG/ o------------------o V_out
PWM o---/\/\/\/--o---|/ Q1 (i.e. 2n3904 NPN)
C1 ===== |
PWM is duty-cycle modulation. Either simple fixed-clock PWM or some
other Sigma/Delta style modulation that has favourable noise
properties, like absence of correlation at audio frequencies.
R1,C1 product determines 3dB rolloff point. At switch frequencies and
linearized around the DC setpoint the circuit behaves as a switched
current source driving a capacitor (integrator). The impedance (R1/C1
ratio) needs to be such that the nonlinear I_BE doesn't influence the
charge current too much.
COMP is comparator input. It can be as simple as a CMOS digital
input, relying on the approximate Vcc/2 threshold. It is used to
signal full C2 capacitor charge to the PIC to update frequency
measurement and allow the PIC to initiate C2 discharge by switching
COMP from high Z to ON.
* To be independent of I_BE, C1 should be as high as possible,
meaning R1 should be as low as possible. The collector load of Q1
is a relatively small capacitor so we don't need to worry about
limiting continuous current (200mA max for 2N3904 ) at least
not for the possible fault of a stuck high PWM output.
The limit is then set by the maximum drive of the PWM ouput, which
is 20mA per pin for a PIC.
R1 = V/I = 5V / 20mA = 250 Ohm = +- 220 Ohm.
Note that if we discharge at a very high rate with PWM stuck high
driving 20mA in the base, the circuit can still go to a max
continuous current that far exceeds 200mA. This however seems
less likely. The extreme of the fault case is PWM stuck high and
COMP (discharge) stuck low or high. So yes, it is still possible
to blow up the transistor due to software faults. If this also
needs to be avoided, max base current needs to be limited to
I_c_max / h_fe_max.
* Setting BW to 200Hz this gives:
C1 = 1 / 2 pi f R = 3.6uF = +- 4.7uF
* The Q1 base current I_BE needs to be compared to the smallest
current through R at the highest I_BE. This is the sink current.
The source is larger due to larger voltage drop. The sink current
is a voltage drop over R1 or
I_sink = 0.7V / 220 Ohm = 3mA.
The max I_BE is max I_c lowered by the transistor beta. For
beta=100 and I_c_max=1mA this is a 300x difference which seems
more than adequate.
* Filter impedance
- Lower bound
The currents computed from max R might need to be lowered to
keep the operating currents resonable. Lowering will reduce
power consumption but increase nonlinearity. 100% sure software
safety needs to take into account max I_c when COMP is tied to
ground (saturation current: 200mA) and max power dissipation
when COMP is tied to Vcc (625mW -> 125mA).
- Upper bound
There is a clear upper bound to impedance as the C1 charge
current needs to be always larger than the max I_BE.
Luckily this meshes well with the PWM being asymmetric, as drive
current is about 5x larger than sing current at normal operating
It seems that to keep the currents 1. safe and 2. efficient they
need to be quite low, exposing the nonlinearity introduced by
* C2 discharge time
The resistance of a PIC output transistor is about 100 Ohms
(estimate grabbed from the web - not in datasheet). We need to
make sure that the discharge time of the capacitor through this
resistance is far below the smallest oscillator period. Also we'd
like to keep the on-time small since it has to be switched
explicitly in the PIC.
With I_c max 1mA at 20kHz / 50us and a voltage range of 2.5V the
capacitance needed is 20nF. This corresponds to an RC time of 2
uS through the PIC output pMOS on resistance. For full discharge
we should take say 5x this time which is abut 10uS.
The capacitance is bounded by the PIC pin capacitance of 5pF so
there is definitely some wiggle room there.
With the 100 Ohm estimate, the peak discharge current at 2.5 is
25mA, which is right on the bound. (Maybe that's where max
current rating comes from?)
The discharge time seems a bit on the high side so we might need a
lower capactance/current configuration. Probably 100uA at 20kHz
is going to be better. This brings the current down very low
thoug: 100nA at 20Hz. I suppose the limit is going to be near the
input bias of the buffers used, which si 65pA typical for
* C2 load current range / C2 value
Are there any bounds on determining the the order of maginitude of
the output current? There is output impedance, which can be quite
high but shouldn't be rediculously high so we have trouble
buffering it or so that transistor and opamp noise becomes a problem.
- Lower current:
Energy consumption, nonlinearity due to I_BE, max discharge
through PIC output pin pMOS.
- Higher current:
Noise, buffer input impedance, buffer bias current.
The thing to find out is, given we need 4 decades and the
resonable largest current range is 1mA -> 100nA, how far can we
lower this to bring the current consumption down and allow for
less dependence on input RC impedance?
I.e. do we want to go much lower than audio and use the oscillator
also as LFO, possibly giving up on precision. The analog part
probably doesn't have trouble with this, but the digital part
might, as it requires larger timers. or even to switch off the
feedback loop entirely.
It seems straightforward: if the I_BE nonlinearity is an issue,
lower the output current. Otherwise pick 1mA. Maybe the
nonlinearity isn't an issue at all since it only manifests at
thigh frequencies where our ears aren't so sensitive to frequency
changes anyway.. Those sounds are mostly used for effects, since
they are not so musically interesting.
* Controller stability
If the non-linearity is an issue, it needs to be dealth with by
making the control loop tighter. Does this introduce
instabilities? The time constant of the feedback loop is mostly
determined by the averaging factor used in the pulse time ->
frequency converter in the PIC.
Might be best to make the frequency exact, but control the