[<<][synth][>>][..]Fri Dec 31 00:25:04 EST 2010
After the fear of opamps and the fear of BJT, now the fear of FETs.
- JFET, V_T < 0. Does this mean that it is really only useful as an
amplifier, biased in the saturated region?
- When does saturation start?
- What about using a JFET as a switch, as I've found in many guitar
pedals. These have signals biased at 4.5V so there is some room
to get the gate voltage low to turn off the switch.
- V_T seems to have quite some spread:
* 2N5457 -0.5 to -6.0
* 2N5484 -0.3 to -3.0
From the CD4049UBE hex CMOS inverter datasheet the voltage
transfer graph also displays similar spread.
See page 123 of TAOE. Accorting to that it's about 2V for MOSFETs
and 5V for JFET. Compare to 0.63V - 0.83V for BJT (200mV), with
( So I guess the JFET input TL071 also has high offset. Yep. 13mV
max vs 3 mV max for LM324 )
How do you design with that?
Some notes about linearizing resistance. See also TAOE p139.
In TAOE the summary is made. When to use FETS?
- High impedance, low current
- Voltage controlled resistor (VCR)
- Voltage controlled current source (VCCS)
- Analog switches
- Power switching
- Digital logic