Sat Dec 25 02:15:39 EST 2010

Combinations of dithered Sigma/Delta and PWM.

Thinking about it a bit more, the problem isn't really periodicities
in the inaudible part over 20kHz: PWM can be used there.  What is
needed is decorrelation of the audible part.  Stacking a dithering
sigma delta modulator on top of a PWM would also solve the speed
problem, as the PWM can be offloaded to hardware while the compute
intensive parts can be performed at a lower frequency.


Suppose we pick a PWM frequency of 10 MHz / 256, which is about 40kHz.
That gives 8 bits precision on level 1.  Level 2 could then add 8 or
even 16 bits more, and has a bit less than 256 cycles to perform the

I.e at 152 Hz we have 16 bits precision, and at 2 second time scale we
have 24, depending on the time scale of the following filters.
Probably don't need that much.

Main goal however is to have more than one output.  Ideally all of the
pins should be usable as modulated outputs.  Dithering can probably be
reused for all channels and performing all the calculations in 256
cycles seems doable, say 16 cyles per channel.  The problem is how to
do the switching itself.

One possible way to make it implementable is to allow some slack in
the output that feeds back into the 2nd layer.  I.e. let's say we try
to make the PWM exact, but always measure the timing register of the
output pin transition.  This should make it possible to spread out the
transitions so they can be done sequentially, but it does requires
sorting of the transition times.

This seems like an interesting idea but can it be made to work?  The
"apparent" non-determinism worries me.  But the general idea seems to
be solid.

Problem: The "large cycle" problem also appears here if the output is
close to the PWM scale crossing.  Maybe this should use some form of
overlaying, such that the SD is only used in 1/2 of its dynamic range.
I.e. loose 1 bit to limit the cycles to period 4.