Fri Dec 26 19:45:48 EST 2014

Small C code

Target: ARM Cortex M.
How to get the smallest code possible?

Using a forth-like approach seems appropriate.  How do native code,
threaded code and huffman threaded code compare?

What is needed to make a huffman threaded interpreter?

One thing is clear: everything needs to be written from scratch.  No
code reuse.

Maybe this is a niche of existence for Staapl?

Essentially I'm still trying to convince myself to not give up the
PIC18 architecture.  Bottom line is that it is still easier to work
with from a hardware pov.

I want too much: both using cool 32 bit cortex processors, *and* being
able to continue working on Staapl.

So what is, again, the niche?

- Code size -> huffman-threaded Forth interpreter.

- RPN macro assembler with peephole optimizer.

The peephole optimizer for PIC18 is working.  Building one for ARM
seems like too much work at this point.