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Wed Nov 9 00:47:15 EST 2011

PK2 sync

I wonder if it would be possible to change the sync part to a level
triggered interrupt, maybe using the same protocol as is used in the
ICD, which is to cause a 1->0 transition on RB6 pin (clock).

This means that we need to keep the bit high in idle, and lower it to
signal interrupt.

I think this even works with the current protocol.

pulse 0:  target writes 1 to ack, otherwise line pulls low.
pulse 1:  target releases bus
pulse 2+: host writes packet, then waits for reply

so instead of expecting a reception after the first pulse, the host
will poll until it sees a 0->1 transition from the target, which
acknowledges the interrupt.  from then on, the fast protocol can be
switched on.



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