Sat Apr 9 18:19:35 EDT 2011
ICSP on 8MHz
Doesn't seem to work. Is this important? Yes.
I tried it down to 200us clock which is ridiculously slow so there has
to be another problem. I can see similar issues at 15us. Some sync
It takes the chip 25us to respond to the handshake pulse, so anything
that's larger that that should be fine. Let's take period 60us.
Problem is: both write to the bus, so it looks like they continuously
get off cycle.
The thing is, that's quite a long time. Is it actually running at 2
MIPS? It's just sitting there in a tight loop of 3 cycles. It takes
5 cycles to get from detection of positive clock level to setting the
output. At 0.5 us cycle time (2 MIPS) that should be 2.5 us, not the
tenfold of that.
Something's not right.
Section 2.4 in the data sheet: at startup, the output of INTOSC is set
at 1MHz. That makes more sense!