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Sun Mar 27 12:45:36 EDT 2011

Reading the ICSP proto on PIC

Trouble is that by default the PK2 sends very narrow pulses: 160ns,
which is 2 cycles at 12 MIPS.

This is no problem for hardware, but for software it's a bit of a
stretch.  Can this be slowed down on the PK2.  Otherwise it might be
necessary to use the KBI2 feature, which is not universal.

RB7 = PGC = KBI2 for the "new core" 18F:
18F2550
18F1220
18F2620
18F24J10

but i.e. not for the "old core":
18F252

for the very new core which has a different data sheet pin diagram,
they seem to be listed as IOC which I assume is the same:
18F46K22

RBIF (INTCON 0) changes when a PORTB pin changes.  The trouble is
going to be that we need to detect only clock edges, not a data edge.
We can't check the data itself because we're not going to be fast
enough..  Triggering on both data and clock should be possible if the
delay is set high enough.  The PK2 is quite predictable: data is set
and clock is toggled as fast as possible, so a small delay after any
data or clock change should be sufficient.

However, it might be necessary to go to SPI or I2C using the extra AUX
line since this seems to be a bit too much foefelare.

Wait: it is possible to change the pulse with by changing the speed
using SET_ICSP_SPEED.






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