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Thu Jul 16 14:05:17 CEST 2009

roadmap

I got a pretty big stack now, started with the idea to port to 6809..
Let's disentangle (goal followed by dependent goal indented).

  * 6809 port + rekonstrukt on the Spartan-3A avnet evl

  * asm - dasm - sim specification  (would also enable dsPIC port)

  * constraint / dataflow specification of a CPU arch (would enable
    proper Staapl semantics useful in static processing: checks + PE

So, how to tackle this?

As I already mentioned before, an example of the problem I'm facing
concretely is how to unify types (very ad-hoc metadata for asm
parameters) with the concrete machine semantics.

I should clarify this and grow the disassembler into a simulator by
figuring out how to represent the two stages: assembly/binary
instruction syntax and run-time machine state operations.




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