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Thu Jul 16 08:46:30 CEST 2009

instruction decoder (asm - dasm - sim)

This assembler business is a serious pain in the ass..  What I really
want is:

  - assembler  (s-expr + forth RPN syntax)
  - disassembler + standard dasm pretty-printer
  - simulator

All generated from the same piece of code.

In some sense, the manufacturer's asm syntax is disposable.  As long
as it can be pretty-printed there is really no need for it.  What
counts is the binary machine code syntax.

The main reasons to include the simulator in the loop are:
  - development of sim+asm/comp itself is made testable
  - partial evaluation will no longer need ad-hoc semantics

Bottom line: currently Staapl is completely defined in terms of
machine semantics and ad-hoc infinite precision eager evaluation at
compile time.  It needs some semantics to at least provide a safety
net for this cavalier way of dealing with compile time computations.

Basicly, there should be only one '+' in the whole chain.

A central piece in this is the instruction decoder.  If it is possible
to write this as a bijective function, a 1-1 map between parsed
opcodes and a binary vector, the rest is just connecting up logic
elements to registers.




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