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Fri Sep 12 08:33:05 CEST 2008

Re: DavidP5 (Microchip forum)

In the following thread:
http://forum.microchip.com/tm.aspx?m=356807

DavidP5:
> So, what you made is a variant of the Forth programming language for
> PIC18s?

Essentially, yes.  That's what is finished now.  But there's a lot
more to it than that, mostly moving in two different directions:

Higher abstraction:

    It is Forth, but with its conventional macro system replaced by a
    functional programming language based on the Joy language:
    http://en.wikipedia.org/wiki/Joy_(programming_language)

    Why?

    * As you already mentioned, functional programming languages are
      good for writing compilers: a compiler is a data structure
      converter == a function.  A tool most useful for this is pattern
      matching:
      http://en.wikipedia.org/wiki/Pattern_matching

    * Due to their similarity, the Joy/Forth interplay makes partial
      evaluation easy to express as simple algebraic manipulation.
      I.e. there is a rule that says that "1 2 +" always can be
      replaced with "3", or more generally for any two numbers
      preceding "+".  The trick is that this mechanism can be used for
      more general template programming.

    This, together with the integration in the PLT Scheme module
    system makes a solid base to start experimenting with different
    languages and domain specific models on top of the low-level
    typeless stack machine language.

Portability:

    The idea is to find a standard set of macros that can abstract the
    microcontroller architecture to a large degree.  This set will be
    based as much as possible on standard Forth and existing stack
    computer instruction sets.  Compared to C this can go a lot
    further because it is based on a macro system instead of a
    function library API as is common for other abstraction layers.

    Staapl contains a (dis)assembler generator that should make
    porting to new architectures relatively straightforward.  I'm
    currently working on 12 and 14 bit cores.

    The step to integrating this with a processor simulator generator
    isn't that big, but this would really need closer cooperation with
    chip vendors as I'd like to do this with machine-readable chip
    descriptions.


What I'd like to find out is how people who spend most of their time
``in the trenches'' would use this tool.  For me it's in the first
place a tool to build things on top of, but I'm quite curious whether
using it just as a low-level machine abstraction layer would work, and
what would need to change to make that really practical.  I wrote some
nontrivial applications in it (a sound synthesizer toy and an ASK/PSK
modem) so I'd say it can definitely be used as such.

For more information, here's some documentation that talks only of the
lower Forth layers:

http://zwizwa.be/archive/pic18-forth.pdf
http://zwizwa.be/archive/pic18-synth.pdf

Cheers,
Tom




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