Sat Aug 9 19:10:37 BST 2008

Staapler protocol

1. Document the ICD2 master-slave protocol
2. Add to this slave->master messaging (maybe just polling?).
3. Allocate pins on master + slave side

1. From the programming manual for 18F1220 (DS39592B)

   Commands and data are transmitted on the rising edge of PGC,
   latched on the falling edge of PGC, and are sent Least Significant
   bit (LSb) first.

   All instructions are 20-bits, consisting of a leading 4-bit command
   followed by a 16-bit operand.  Depending on the 4-bit command, the
   16-bit operand represents 16-bits or 8-bits of data.

   COMMANDS FOR PROGRAMMING           4-Bit Command

   Core Instruction                   0000 (Shift in 16-bit instruction)
   Shift out TABLAT register          0010
   Table Read                         1000
   Table Read, post-increment         1001
   Table Read, post-decrement         1010
   Table Read, pre-increment          1011
   Table Write                        1100
   Table Write, post-increment by 2   1101
   Table Write, post-decrement by 2   1110
   Table Write, start programming     1111

2. The hardware protocol used is really enough to provide
   bidirectional communication if it is extended with a simple 'data
   ready' signal from the slave.  This could either be an
   asynchronous slave signal (pull a line low/high) or an answer to a

   A direct slave signal is probably easiest to implement.  Then it
   should be the data line since that is already a multiplexed port at
   the master, leaving the clock to remain output-only.

3. On the slave side it's easy: use data and clock from the
   programmer protocol.  On the server side, the clock will allways be
   output, but the data line receives an asynchronous signal.

   In case of asynchronous signalling, the data line is probably best
   implemented as a wire-or bus.

   Slave side data line for 18F1220 is RB7.  It has a weak pullup;
   maybe this can be used instead of on the master side, i.e. thinking
   about driving with PC parport, which has open collector output?
   This http://www.beyondlogic.org/spp/parallel.htm suggests using a
   4k7 pullup.

   target        host
   PGC           RA0
   PGD           RB0
   PGM           RA1
   VDD           RA2
   /MCLR         RA3
   GND           GND


It's probably best to start with reading the device using the ICD2
protocol.  That way core routines for write and read can be created.

The return protocol is self-delimited: each return message is
prepended with the size of the message.  Probably the master->slave
protocol should do the same so it can be routed.

RB7 is slave data line; sending is a simple shift.  Same for RB0
master sending.

What with Microchip's in circuit debuggin protocol?  Is that specified