Thu Jun 5 14:05:22 CEST 2008



What I need is a language for simulator design, or more specifically,
a strategy for compiling target code + some semantics spec to host
executable C code for optimal performance.

An advantage is that what needs to be simulated is usually quite
lowlevel code with fairly specific space and time characteristics. So
basicly, a state machine description language is necessary. Something
that can be compiled to a massively parallel C program.

If there is one place in Staapl where partial evaluation is going to
make a big difference, it's there.


Instead of writing a simulator, building a partially evaluated
simulator might be a better idea, since for simulation speed is very

What is an instruction? It's a state update. state is memory. Memory
is a number of registers, with variable bit size. So an instruction is
something with the following properties:

  * an endomap for (a subset of) the machine state
  * timing information
  * encoding (for instruction interpreter)

Maybe i should take a step back towards pure s-expressions for
instruction set spec, since these are a bit hard to compose (write
macros that expand to them) composition would help to define some
instruction classes.

 (addwf   (f d a) "0010 01da ffff ffff")

 ((addwf f d a) ((#b001001 6) (d 1) (a 1) (f 8)))

Actually, the simulator descriptor language is as good as the same as
the dsp dataflow language. maybe i should do the latter first, then