Sun Nov 14 11:30:46 EST 2010

Staapl and RISC machines

From an implementation perspective a 2-stack machine model allows for
a very simple low-level code generator which is mostly just a peephole

Note however that while this works very well for a chip like the
Microchip PIC18, a many-register machine like ARM or MIPS probably
requires a "real" compiler with more aggressive inlining and register
allocation if execution speed is an issue.

Staapl is side-stepping this issue by concentrating on code size as
opposed to execution speed.  Forth-style programming can lead to very
dense code at the expense of having to think a bit harder to encode
your problem and factor it appropriately.