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Wed Apr 8 15:52:17 CEST 2009

Restating Goals

Before restating the new goals, I'm going to list the things that are
no longer part of Staapl objective:

  - DSP / dataflow code (moved to the IP project).

    The reason for this is quite straightforward: dataflow
    representation exposes parallelism and implementation is mostly
    about the interaction between memoization and code/block
    sequencing: how to keep track of intermediate results given a
    certain memory hierarchy.

    Concatenative code is inherently _serial_ in nature, and execution
    context is easily swapped, which makes it more suited for a
    concurrency oriented programming model.

    It might make sense to use concatentative code as a
    _specification_ language for DSP operations by translating it into
    dataflow representation, but that is not the goal of Staapl as of
    yet.

So, what are the goals:

  + Understand modules in a language without local names.  This has
    been the most important problem in using Staapl's Forth to write
    applications.  Almost all generic code will have macro form and
    directives about instantiation.

  + Investigate bottom-up (safe) language design and verification
    rooted in concrete machine semantics and compile-time checks for
    language abstraction (typed macros).

  + Find a meet-in-the-middle (MIM) model for small microcontrollers
    based on concrete semantics.

  + Find the border between a) static semantic relations relating
    concrete machine, through MIM model to higher order static
    functions and b) dynamic behaviour which is interaction with
    memory and communication with external events/devices/machines.

  + Optimize the MIM model for FPGA implementation.


Some of these terms are a bit vague, but I hope the general idea will
become more clear later on.




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