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Sun Jan 26 05:36:17 EST 2020

FPGA

What am I missing?

First, the CSP style concurrency is fundamentally different from
synchronous logic.  Maybe work a bit to bridge the gap.

Say I want to write a SLIP decoder as a sequential program, and
compile it down to a state machine.  This is non-trivial

loop:
  read
  - case ESC:
      read
      case ESC_ESC
      case ESC_END
      default
  - case END
      send PACKET
  - default
   
     
Yeah I'm really stuck at things like this.  What does it require?

- Map events to signaling conditions

- Change tasks to update functions / state machines

That should be it: no transition when there is no event, and if there
is one or multiple events, perform a tie-breaking operation.




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