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Fri Jan 24 07:04:48 EST 2020

Rendez-vous in hardware

Simplificatation:
- Direction is hard-coded
- One reader, one writer
- Synchronous logic only

Eiter one can arrive first.

Sender:
- Sets output signals, raises write
- Waits for rendezvous signal
- Lowers write, continues

Receiver:
- Raises read
- Waits for rendezvoud signal
- Samples, lowers read


If the reader is first, to the writer this should look the same as
sending out a non-synchronized pulsed write.  This way we can still
use non-synchronized feeders whenever we can guarantee that the reader
is always ready.  Sync can be removed as an optimization.

Googling.  Not directly related, this is for async:
http://async.usc.edu/jungfrau_web/htdocs/new/research/current/verilogcsp/VeriloglCSP.pdf





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