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Fri Jan 24 06:59:40 EST 2020

Reiterate FPGA bits

So thinking in CSP style cuncurrency, what can be done on the FPGA?
What is missing in my understanding to make this completely natural?

E.g. writing state machines as communicating processes is now obvious.
The same could be true for FPGA.

Maybe the secret is in select?

1. Receiver being able to handle a number of things at once

2. Sender blocking until receiver has message

Up to now I've been really focused on sender controlling the transfer:
outputting a sync pulse, requiring receiver to be listening.  This is
not necessarily true.

Ok that's clear: focus on rendez-vous.



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