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Haskell DSL for synchronous circuits



20200605 z transform
20200319 mini cpu
20200216 next
20200214 applicative notation
20200213 Substrate nesting
Programmable datapath
20200212 clock domain crossing
20200210 Testing memory readers
20200208 ISA generation
20200207 Substrate independence
20200206 Bit-serial Forth processor?
Accelerate
Sharing
Why am I not using other tools?
20200205 Why is TH necessary?
Make tests easier
20200203 general remarks
channel: examples
General remark about 'close'
Channel, final word?
Asymmetry in read/write
More handshake examples
20200202 Port transaction symmetry
20200130 UART revisit
DMA
Change of style
Truth tables
testing rendez-vous
20200129 rendez-vous
20200128 How to make this understandable?
Syncrhonization example
A good book on circuits
Practical example
Justify "applicative" structure
Rendez-vous: ready + ack
Pulse vs. level
Handshake
DMA
Synchronization
20200127 integrate with fusesoc
Synchronization
Memory reader
channels
Modify deser to be able to do 2-bit sequences
20200104 Erlang as CSP substrate
20191222 Compiling CPS state machines
Next state spec
20191213 C-like lang
20191209 Buffer reuse
20191208 Move structure into names
20191207 Example?
How to actually do that? Phantom types.
Implementation / Specification codesign
Method: project model onto specification
Sequential programs are not natural
Transformation of parallel to serial?
buffers over fifos
logic implementation is about deforming time
buffers
20191130 Sequential programs are the norm
20191128 DSP
20191115 I need a hello world
An s-expression front-end
state machine language
20191111 a state machine language
parallel, time
20191109 Abstract DHT11 driver
Events on FPGA
DHT11 state machine
20191018 Practically, what does that substrate look like?
Dataflow
20190922 Shared substrate
20190830 Pipelining
20190824 8 instructions
20190818 Coroutines
20190817 Try out ABC: give it a LUT
State update representation
A generic data converter architecture
FSM extraction and boolean function optimization
Figure out how yosys passes things to ABC
Sumary of ideas
Common subexpressions
The higher level language
Pipelining is the real problem
Transactions vs. Flip-Flops
20190815 Protocol splitters
The CPU attractor
20190814 Notes
Lets start with a state machine synthesizer
stat should be local in both place and time
Make FPGAs and CPUs the same
20190813 State machines
Interface to Verilog
20190730 Compositional state machines
Meta-programmed Erlang node
20190602 partial application of grids / grids as finite functions
Cleaning up the language
Structure of the language
20190601 loop :: (i -> M t) -> M (A t)
20190531 traverse vs. construction?
20190530 feldspar
Can it just be a functor?
It's time to crack the nut. What is loop?
20190529 Next
20190528 Am I looking at this the wrong way?
c <- a i j
Next
20190527 Bounds checking
References
20190525 Move forward
20190523 What do I need?
20190522 Next?
20190521 LLVM diff
Indices
State + Reader
20190520 State Continuation Threading
Pause
State Continuation
All .hs code in ~/darcs/meta
A monadic test language
20190519 Revisit

grounding
How to modify escape analysis?
I'm going to need register allocation as well
accu matcher
20190518 Next
Ranges : loop indices are really just sizes
Fix the representation of definition and use
Triangles
Accumulators
20190517 LLVM loop optimizations
accumulation
Different intermediates
Escape analysis
20190516 Escape analysis
Local context
Use the fold
20190515 Next
About folds
Expressing the operations
20190514 LTA
20190512 summary
Loop algebra
Construction of loops
Identifying reuse patterns
Escape analysis
Grid
Feldspar and fused representations
Moving forward on the loops
20190511 Implement some loop
20190510 Make arrays total
Type level stuff
20190509 Next?
Lambda
Random access
20190508 Context
Map/Fold
20190504 holes
Two-pass full array + triangle feedback
Go back to RAI
zipfold
20190427 zipfold
20190422 Summary: SeqLoop
Primtives with multiple return values
C.hs
20190421 Necessarily Meta
Loops are environments
Target vectors
Test case for implementable vectors as loops
Abstract representations of vectors
Base ring/field
Next
20190420 System solving
Z-transform, summary
Z transforms
Lists and Functor, Traversable, Zip
ST
Bridging the two systems views
Why is this uninituitive?
The problem is commutation.
An example
Parameterized Z-transform
Ring vs. System
Start with Ring
The DSP language: combinators and algebraic substrate
Extend types gradually
20190419 Avoid "inferring"
A driver application: quadrature tuner
Better signal type
Combine Seq and EDSP?
20190411 Make probe names hierarchical
20190410 Registers and commands
20190409 Don't try to abstract muxes
Parameterized decision table
Traversable, Zip
Imperative construction of circuits
Multiplexers
20190408 Test circuit
Dynamic probe names
Naming: enable / strobe / clock?
contravariance
20190407 The low level monad
Tree vs. Path representation
How to get used to large I->O functions
20190406 Designing hardware with a control CPU
Compile to ST without TH?
alright, revolution!
20190405 Rekindle the fire
Process: why is this still hard?
State machine composition
RAM as decoder
Look at the geometry of the problem
Sequencers
20190327 Higher level abstractions
20190320 SERV
20190205 Syntax frontent
20190115 ecosystem integration
20190111 CPU
20190109 Think compositionally
Off-by-one
reset behavior
20181228 pizza dinner hdl
20181215 bitserial CPU : SERV RISCV
20181202 Next
20181128 Setting up dev env for CPU tests
20181103 Tradeoff: blocking read vs. exiplicit bit wait
20181031 Verilog frontend
ports vs. bindings
20181026 Simulating protocols
20181025 Test with memory contents
Memories
20181023 uart TX
bus reads
uart bugs
20181021 wanda update
Update tools?
20181020 Pipelining CPU
20181018 Premature opti
Cont...
Bit sync
20181016 The solution is factoring
State machine
20181015 Verilog
Behavioral
Imperative vs. functional
State machines
20180928 State machines vs. processor
20180916 Architecture
dsPIC
SAT/SMT: stick to z3 for now
PRUs and instruction counting
20180914 So, what about just using assembly?
20180913 Instruction scheduling using SAT solver
20180908 Emulator / Assembler
20180907 I'm a little stuck
Next
20180906 Code gen or scaffolding?
PRU revisited
20180905 CPU Emulation
Next
PLL
20180904 Next
cosim next?
cosim
20180903 bug?
cauterize
VPI
20180902 Abstract submodules
20180901 Verilog
20180831 Low-hanging fruit
Verilator or Icarus?
tristate logic vs. multiplexer trees
20180830 Direction: work with existing Verilog code
20180828 Verilog gen: names as strings
Scan
20180827 Zip CPU
iCE40 VGA demo?
Timing
20180826 post synthesis changes
Publish?
iCE40UP5K
Generic assembler
Cleaned up module structure
Behavioral is NOT state machine synthesis
simple tests
Verilog cosimulation
Sequencers: state machines vs. CPUs
20180824 Verilog next
20180823 concat
Processor as a macro
Update: behavioral
Record assignments
Procedural / behavioral modeling
Chisel HDL: the latest instance of a flawed approach
structured programming
cosim
20180822 Macro languages / Simulation
Something else
Verilog
20180821 Next? Verilog done.
20180820 Next? Verilog
SeqNetList
20180818 Unification
Spiral after focus
Term type cleanup
Behavioral
Next?
Verilog FPGA test
Unification
Failing tests
Verilog debugging
PLL
Avenues
stripping bare a 6809
Xylinx lava
Clash, Lava
yosys log
20180817 RTL
STUArray
Verilog
Better testing of CPU
CPU/PLC vs state machine
Bit serial architecture.
Bit-serial CPU, PLC
Forward declarations
Next
20180816 Removed old notes from CPU.hs
How expensive is the stack?
A CPU: It's inverted
CPU designs
variables
single stack is enough for a control processor?
Subroutine call / return
soc spi
Better instruction packing
CPU resource use
Lessons Learned
Bitbang UART vs. hardware
So CPU works
Why do FPGAs use LUTs?
Generate verilog directly
I can't slow it down?
FPGA SPI bug
How do you call a clock enable pulse?
Buffer
State machines
Smaller step
Debug probes
deser
20180815 State can linger.
No sign of life for CPU
FPGA board test
Next
iceprog
PLL setup
FPGA load program
Yosys ram init
Build cleanup
MyHDL is picky
rle
critical path
20180814 FPGA reverse engineering
Sizes of things
Bad hex value 1ff
Tests
A Forth
Instruction Sequencer vs. State Machine
Low hanging fruit?
next
MyHDL code gen cleanup
MyHDL
20180813 Memory instantiation hierarchy problem
MyHDL test bench
MyHDL concat
Memories
Into the real world?
20180812 State machine vs. instruction sequencer
Loops
Next?
CPU startup
Yosys FSM Detection
Synchronous SPI
MyHDL RAM
Path to FPGA
UART out on bus
Next?
20180811 Probe
CPU hierarchy
MyHDL memories
Read ready, streams
Busses, cont
CPU bus
Focus more on composition
Testing uart transmit
20180810 Assignment language
output to input dependency?
Next?
Variable names
Check yosys output
Now here's an other idea.
SeqTerm and blocks
Figure out conversion to nested if elif else
async_transmit
Blocks
20180809 Display
bit-serial architecture
bundling case
async tx
Reset is not implemented properly for SeqTH
CPU, sequencer
20180808 applicative style and instantiating spaghetti networks
Indexed muxes
closeMem
20180806 Keep pseudo ops
Pru emulator
20180805 Stacks
CPU design
Write-through delay for FIFO and stack
FIFO / Stack using grey code
Here's a big lesson
Sequencer
Memory init
Hardware is annoyingly pure
Building a CPU
Unify
20180803 seqInitMem
20180802 arrays
mode 0 spi
Behavioral vs. RTL
A driver...
parallel if
20180801 custom quasiquoter
20180731 Logic analyzers
Interesting avenues
LLVM
Logic analyzer
20180729 uart-controlled clock enable
20180728 Next
Why can't primitives be pure?
20180726 Next?
Next?
20180725 SeqTH / SeqPrim
20180724 Monad laws
Applicative sharing
The point
Upside-down : the dual implementation in terms of type families
Sharing
pure / applicative
20180723 TH
Fix emulation inefficiency
20180722 Blink-a-led working on breakout
Applicative
Kleisli arrows
20180721 Arrow
signal/next and memory/nextMemory
The mapped if'
Memories..
20180720 FIFOs
20180719 Bit sizes as types
more UART
20180718 UART debugging
Logic simplification
MyHDL case statements
20180717 State machines
UART
Shifts
QC generators
Testing tagged streams
RTL misconceptions
Enabled streams
20180716 Slowing down state machines
VHDL and synthesis
Conditionals, again
functional dependencies
Conditionals
UART
Environment
subsample, when
UART and sub-clocking
Clocks, RTL
Practical stuff
20180714 Seq, what does it do?
nailing down semantics
20180708 DSL, sharing and monad laws
20180707 put this to the test?
Named ports
MyHDL sim test
20180706 PruEmu
20180619 Got it: existential + dynamic types
ExtStates
20180618 Stacking monads
20180617 Practical
Applicative
MonadFix?
Kleisli arrows
Arrows?
20180616 Push a stack
latches / registers and pure functions
Preinc/postinc access
20180614 Haskell / Python bindings
20180611 parsec + template haskell?
Make a test bench for semantics
MyHDL output
20180610 Trigger filter
SeqTerm SType
concat
20180604 myhdl interface
20180530 CPU, sequencing
ZipList
Why is there a pipeline delay?
regFix bug
20180529 I don't understand Free
Allow non-monadic Seq constants
20180528 State, revisited
Memories
signal and next
Patch two "coroutines"
20180527 Memory emulation
Encode signal types as types?
Free Monad
fanout
MyHDL
20180526 RAM
Inputs?
(s,s->s)
Traces that do not have generators
Conditionals
Renaming RTL to Seq
Export a module
Wire transposition
Reset value
Is it necessary to model wide signals?
fix instead of next?
Remove combinatorial drive?
It is very annoying not to have constants
20180525 RTLEmu
Arrow / Category
Abstracting fix?
Generate signals
fix?
Signals
Basic idea
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