Mon Feb 3 08:05:14 EST 2020

General remark about 'close'

When closing multiple operations at once, it becomes a bit arbitrary
in which order these are performed, and also there is quite a bit of
shuffling needed to bring outputs out of the circuit being closed.

In Verilog this is a lot easier to do by just defining a bunch of
registers and using assignment to perform the cross-wiring approach.

So is it worth it?

This seems to be what is payed to keep an applicative interface.

I'm going to assume for now that yes it is worth it, becaue it makes
abstraction cheaper.

Let's put it in the README.