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Mon Feb 3 07:55:35 EST 2020

Channel, final word?

-- We break symmetry based on the requirement to not have a data delay
-- as part of the loop closing operation.  This makes frontend=write,
-- backend=read.
--
--   /-------------------<----------------------\
--   \-->--[D]-->--[f:write]---->--[b:read]-->--/
--                    \--------->-----/
--
-- This brings us to the following implementation.
closeChannel writer reader = do
  closeReg [bits 1] $ \[d_rd_sync] -> do
    (wr_sync, wr_data, wr_out) <- writer d_rd_sync
    (rd_sync, rd_out)          <- reader wr_sync wr_data
    "d_rd_sync" <-- d_rd_sync
    "rd_sync"   <-- rd_sync
    "wr_sync"   <-- wr_sync
    "wr_data"   <-- wr_data
    -- wr_out, rd_out: other state machine outputs not necessarily
    -- related to channel communication.
    return ([rd_sync],(wr_out,rd_out))





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