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Sun Feb 2 19:55:41 EST 2020

Port transaction symmetry

I factored out the read and the state machine.  The SM now takes a
'cont' and produces a 'have'.  This is essentially read and ack.

So it appears I'm re-inventing bus transactions.

1. The core idea is that a read (write) command is an interplay
   between two signals:
   - read end will issue a 'req'
   - write end will respond with an 'ack'

2. The req->ack path is combinatorial at the writer end

3. The ack->req path is combinatorial at the reader

4. The composition of the two inserts a delay on the ack to break the
   loop.


This doesn't seem too hard.  Now why is it a-symmetric?  Can we have a
writer sending the req, and the reader sending the ack?

The insight is that this is already symmetric.  The assymmetry is just
in the names!

This means that this could be a 2-way read/write as well.  The
handshake just defines a moment in time when both are watching the
i/o.

So what to do with this?  Make some drawings on paper...

The symmetry is important.

And the fact that the delay breaks the symmetry is also important.

I'm tempted to split that delay in half!

Go into this: 
There are also combinatorial signals at play for maximum performance.
https://en.wikipedia.org/wiki/Wishbone_(computer_bus)


EDIT: So how do I test this?



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