Thu Jan 30 08:18:40 EST 2020
So I end up very naturally at truth tables. In some cases it is just
very hard to express a transition function in terms of manually
factored binary and,or,not.
EDIT: Since there is currently no direct way to implement truth
tables, I'm resorting to manual implementation.
I do wonder: Verilog has don't care matching, right?
I probably should implement this.
EDIT: It's not really necessary atm. Factoring can actually be
beneficial for understanding. E.g. try to identify local signals that
are meaningful enough to give a proper name, and include them in the