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Tue Jan 28 06:51:27 EST 2020

Rendez-vous: ready + ack

This is necessarily two-way.  Let's break the a-symmetry for now by
requiring that reads will wait for writes.  Then later it is probably
clear how to restore the symmetry.  Essentially this is about agreeing
on a time event.

That statement actually contains the solution.

The output of the synchronizer is a single cycle pulse.  Can this be
constructed from a reader and writer level signal?

Let's go back to a-symmetric case:

1. Writer signals that data is ready by creating a 0->1 transition and
   holding it there.

2. When reader is ready to perform the read, it will generate a 0->1
   transition, and at the same time sample the value.

The action of 2. should acknowledge to 1 that it can continue, but
also remove the condition immediately such that the reader state
machine doesn't read again in the next cycle.  That bit seems to be
the essence.

I think I'm re-discovering interrupts.

Essentially, this is a counter.


If the reader sees the interrupt, it will immediately (and only in
that state!) output a received pulse.

The writer will be waiting for this pulse.  If it is seen it should
immediately turn off its enable signal.

This 2-way thing is tricky.

Let's put in some requirements.

W: . . x x x x . . .
R: . . . . . x . . .
S: . . . . . x . . .

I think the key element is that the ANDed signal is not registered:
information flows in the two directions in a single cycle.

I.e. this makes it easy to generate by the receiver as a side-effect
of the "cond" case that sees the input signal high, and the writer can
see the pulse immediately and lower its write signal for the next
cycle.

So, summarized:

- writer has a wait state where it has the output ready signal raised
- reader has a state that sets the ack pin NON-REGISTERED
- in writer's wait state, the ack pin is used to transition to lower the ready signal

This should work for a continuous stream of readies.  E.g. if writer
doesn't lower the ready singnal, reader will treat it as a next sync.

Summarized even more:  Ready -> Ack path is COMBINATORIAL.

If it is combinatorial, single cycle transfers are possible.  If the
signal is pipelined, some more work is necessary to avoid duplicates.
So definitely this case is simpler.

Also, if single cycle transfers are possible, this is exactly THE
mechanism by which to factor machines into a composition of smaller
ones.






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