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Sat Dec 7 11:07:29 EST 2019

logic implementation is about deforming time

basically: buffering, sequentialization and pipelining

Note that this is really about dataflow, wich is the only thing I ever
need an FPGA for: communication, and possibly some stream processing.

To make this work, set up some interfaces.  The main missing component
is a control flow mechanism for FIFOs.

Ideally, manage the "coarse" time scale of the FIFO in some other way.
This is not typically called a FIFO, but a buffer: one machine fills,
then only when full a buffer is transferred.  However it is still
possible to use only streaming access on the buffer.




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