Sat Dec 7 10:46:43 EST 2019
So I have "clocked words", some signals that have a "valid" signal
associated with them to indicate events.
How to extend this to buffers? Buffering seems unavoidable, so make
sure there is a good strategy.
This is the "control plane vs. data plane" pattern that always comes
up in implementation.
The data plane can just be memories.
So, conclusion: It is sometimes hard to see in the overall design
which streaming connections should be buffered. For non-random access
(FIFOs only), this is an implementation detail that has to do with the
sequential decomposition of some processor. If sequential
decompositions do not line up, buffering is needed to "deform time".
So can it be kept abstract?