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Fri Aug 30 08:16:52 EDT 2019

Pipelining

So it's quite clear: my problem with digital logic is the pipelining.
There has to be a way to express things such that the feedforward part
can be separated from:

- decoupling/pipelining delays
- simple state machines

It's because there are two elements here.  I've already noticed that
factoring state machines makes them easier to understand, as this
allows concentration on stream processing.

But pipelining delays are a real pain.  It already starts with
defining small state machines.  Should the output be registered or
not?  The answer is that it depends.  For high speed logic it is
usually yes.  For low speed, efficient use of gates it is usually no,
or mostly not until timing gets violated.

A thing to keep in mind is to write systems in a way that it is easy
to add delays in the path.




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