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Sat Aug 17 09:37:47 EDT 2019

A generic data converter architecture


Note that allmost all code I write can be implemented as feedforward
chained state machines with some buffers inbetween.

E.g:

I -> b -> C1 -> b -> C2 -> b -> O

- Where each b is just a dumb circular buffer
- Cx is a converter state machine (parser + printer)

What happens where is not important.  Some C's could be on
microcntrollers implemented in C, others could be FPGAs.

But the general idea is that _testing_ should be completely contained.

Also, some buffers are not there at all.

Also, buffers can be abstract, i.e. they can be made to contain
tokens, not bytes.  That way the representation can either make smart
writes or smart reads.




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