Fri Apr 5 16:35:50 EDT 2019

RAM as decoder

A decoder is typically an "expansion", e.g. a small word fans out to a
lot of control lines.  A ram already has that structure: 8 address
bits to 16 data bits.  Maybe that is done intentionally?  I.e. it is
wide by design?

Can it be made wider?  Yes, by chaining 2 RAMs.

Can it be made wider using only a single RAM?  Yes, by multiplexing.
E.g. two 7->16 bit maps evaluated using two clocks.

When is this more efficient than using LUTs?