[<<][rtl][>>][..]
Wed Jan 9 11:42:07 CET 2019

Off-by-one

It remains a real pain to navigate pre/post delay signals.

It seems that a good way to go is to assume this will be wrong, and
always use some kind of redundant assert.

Digital design is really about pipelining.  If it were just
combinatorial logic, it would be easy.




[Reply][About]
[<<][rtl][>>][..]