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Wed Oct 31 09:38:39 CET 2018

Verilog frontend

To make this evolve and integrate into other tools, it will be
necessary to expose modules as readable verilog.

From the Haskell side, it might mean that there is a need for a syntax
frontend, to at least be able to carry node and register names into
verilog, and also have something resembling design hierarchy.





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