Wed Oct 31 09:30:59 CET 2018

ports vs. bindings

There is still an awkward point in how abstraction works: I would like
to bundle inputs and outputs (e.g. an RS485 line with controls), but
how to do this if I and O are always spit as arguments to submodules,
and bindings of return values?

Maybe the solution is the same as ever: abstract things as functions.

To make it more concrete, it might help to write an actual flat FPGA
toplevel to use the same API as a nesting of component instantances.