Tue Oct 23 16:06:45 CEST 2018
Important to realize that there is a 1 cycle delay between bus reads
and values being ready.
read:4 1 0 1 1 (1636x)
read:4 1 1 1 1
read:4 1 0 1 1
The delay comes from:
-- Couple bus master and slave through bus registers.
closeReg [bit, bits imem_bits] $ \[rStrobe,rData] -> do
bus_wr <- bus_master (BusRd rStrobe rData)
(BusRd rStrobe' rData', soc_output) <- bus [rx, tx_bc] bus_wr
return ([rStrobe', rData'], soc_output)
I did this by accident. But is it really necessary to have this
delay? It will make the CPU critical path longer, but have the
advantage that reads take only once cycle instead of two.
It doesn't seem to be an issue at this point, but good to keep in