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Sat Oct 20 15:06:24 CEST 2018

Pipelining CPU

Just fetch.  Essentially this delays the address register.  Everything
stays the same, apart from jumps going into effect one instruction
late.  This then creates a branch slot.

This then takes the RAM access time out of the timing loop.  EDIT:
Looking at this again, the RAM access is only a small part.  Bulk
comes from logic levels (17 deep!).




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