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Thu Oct 18 15:28:23 CEST 2018

Cont...

I have all the components.
- Sub clock counter -> bit clock out
- SR + addr gen + RAM

The problem is reset/enable or start/stop: mostly about how to define
the protocol.  These are roughly equivalent, but require some small
state machines to convert.

- Single enable/nrst
- Start/Stop single clock pulses
- Start/Stop stretched pulses

polarized edge detect can convert:
  stretched -> single
  en/nrst -> signle

( see next post) 
So, for bit sync, which is easiest: start/stop or enable?

Start/Stop is not enough.  States are:
- start, but wait for first edge
- ...

So basically, there are 2 start signals:
- frame start
- first edge after frame start

To solve:
- first start pulse -> enable (or use enable in first place)
- edge pulse masked by enable, then "debounce" start pulses

It seems simplest to use a single "frame" or "chip select" style input
to the circuit, and have the end reset everything.  Bits can be
clocked in as long as frame is high: it will just be an extra couple
of words.

So, general arch:
- 2-stage start/stop (frame start, then first edge)
- frame stop = reset

It seems that the 2-phase start is really the problem.  Inner circuit
should be written to take a single start pulse, and start counting
right away.








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