Mon Oct 15 11:55:02 CEST 2018


Create a behavioral language.  Essentially, this separates variable
declaration and assignment.  It can then still be determined whether
to use single or multiple assignment.  No assignment means to keep the
existing variable.

Is it possible to replace clock tick by "goto"?  This way, everything
executed between these is combinatorial.  That is the backbone.

A state machine is something that can change the value of outputs
(registers) between gotos, using the new values of inputs (other

The main "programming principle": In this particular case, it is more
convenient to think in terms of and express changes in state than the
recomputation of state.

This model is not a perfect equivalence, i.e. it is not possible to
reuse logic in the same clock cycle.

Early exits should be implemented, i.e. multiple in branches.

If partial updates are so important, are clock enables on the
registers then used to implement this?  Do I need to worry about this
in how translation to vhdl will work?

Is it possible to use behavioral description as the bottom
abstraction, and implement the "functional" logic style on top of it?