[<<][rtl][>>][..]
Tue Sep 4 12:30:02 EDT 2018

Next

- Test CPU Verilog on FPGA

- Use Verilog as top-level composition.  Do this for reset gen, PLL,
  ram init.

Most of this is "boring" work.  I need to be more careful spending the
will power to do those things.  Lot's of payed work to do as well..

EDIT: I'm stuck with just boring problems.  I need something
meaningful.  Or somehow awaken the flame.




[Reply][About]
[<<][rtl][>>][..]