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Mon Sep 3 21:33:41 EDT 2018

bug?

reg [7:0] p0; // (0,Free (TypedForm {typedFormType = Just 8, typedFormForm = Input}))
reg [7:0] p1; // (1,Free (TypedForm {typedFormType = Just 8, typedFormForm = Connect (Pure 2)}))
wire [7:0] s2; // (2,Free (TypedForm {typedFormType = Just 8, typedFormForm = Comb2 ADD (Pure 0) (Pure 2)}))
assign s2 = (p0 + s2); // (2,Free (TypedForm {typedFormType = Just 8, typedFormForm = Comb2 ADD (Pure 0) (Pure 2)}))
assign p1 = s2; // (1,Free (TypedForm {typedFormType = Just 8, typedFormForm = Connect (Pure 2)}))

that 4th line is wrong
it looks like the constants start counting at the wrong offset.

Yes... should be 1 + maximum.

It's likely that this is the bug I've been looking for.  Nasty enough to mess up a network.

EDIT: .v code gen works on FPGA now.




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