Sat Sep 1 08:47:42 EDT 2018


Maybe leave the cosim out of the picture, but make a working verilog
RTL gen.  What is missing currently?  Likely the problem is the

EDIT: What's needed is a cosim function, that returns the Seq
emulation, but also the Verilog one.  This seems like a lot of work,
really.  How to split it up into manageable parts?