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Fri Aug 31 21:26:32 EDT 2018

Verilator or Icarus?

MyHDL uses Icarus, so that's what it will be.

Just do what MyHDL does:
http://docs.myhdl.org/en/stable/manual/cosimulation.html

  module dut_bin2gray; 

     reg [`width-1:0] B;
     wire [`width-1:0] G;

     initial begin
        $from_myhdl(B);
        $to_myhdl(G);
     end

     bin2gray dut (.B(B), .G(G));
     defparam dut.width = `width;

  endmodule

And use the "probe" mechanism to send the probe signals back using
to_x, and push in the test signals using from_x.


http://iverilog.wikia.com/wiki/Using_VPI


So there is a straightforward path with MyHDL as an example.  It
involves a lot of reading, so not for now.





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