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Mon Aug 27 00:31:11 EDT 2018

Timing

Maybe more important than verilog, is to get a better handle on timing
constraints.  E.g. how fast does the CPU run?  Is it fast enough for
the application, or do we need multiple clock domains?

As I mentioned before, I find it strange that I don't run into timing
issues (yet), while this is the main thing in all other CPU designs!

Path:
verilog -> pll instantiation -> CPU test




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