Sun Aug 26 12:04:45 EDT 2018

simple tests

But first, some simple tests.

E.g.: a test that writes to memory, reads it out.  Basically it would
be nice if this could be expressed such that it can be plugged
directly into the existing QC functionality, while also allowing
inspection of the generated verilog.

EDIT: Postponed to later.  This is too much "work".  The MyHDL path
works for the CPU, so use that for now.  Work on this in the