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Sun Aug 26 11:20:09 EDT 2018

Verilog cosimulation

I started some basic testbench work.  Ultimately, I want cosimulation.
IVerilog can do that.  So maybe go for it straight away?

How is the interface built up?


root@zoo:~# apt-file find iverilog
...
iverilog: /usr/include/iverilog/_pli_types.h
iverilog: /usr/include/iverilog/acc_user.h
iverilog: /usr/include/iverilog/ivl_target.h
iverilog: /usr/include/iverilog/sv_vpi_user.h
iverilog: /usr/include/iverilog/veriuser.h
iverilog: /usr/include/iverilog/vpi_user.h
...

iverilog has vpi_user.h which refers to this standard:
https://en.wikipedia.org/wiki/Verilog_Procedural_Interface


What I need is either message passing, or calls from iverilog into
Haskell.  As a direct FFI, calls from Haskell into iverilog would be
more appropriate, but likely a bit awkward.

An example would be nice.

http://www.asic-world.com/verilog/pli6.html
What is a system task?

It seems to be a function that is called inside a begin/end block.
How do I get at wire/reg values?

I want to simulate something where the i/o relation is implemented on
the Haskell side.  It seems that just calling a function from verilog
is enough.  Is this a "system task"?  Something that can take
arguments and return them?







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