Thu Aug 23 01:33:43 EDT 2018
Chisel HDL: the latest instance of a flawed approach
Since we are constructing a digital circuit, the notion of
reassignment does not make much sense since connections between
circuit nodes only need to be specified once.
This is a puzzling statement. It would suggest that Chisel reduces
the goal of an HDL to structurally constructing a circuit. What
about describing behavior, which is the main reason why industrial
HDL designers use VHDL, Verilog, SystemC and MyHDL?
So I'm making the same mistake. Jan mentions again that merely
constructing circuits is a mistake, and that behavioral modeling is
the important property.
I've actually run into this, to be honest. Why am I building a CPU?
To be able to do sequential programming.
In the comments, Jan comments on blocking assignments: