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Wed Aug 22 12:35:36 EDT 2018

Verilog

Easy to do huh?

Quoite a detour to make SeqNetList.hs and still not generating the
f_soc example properly.

It works for f_blink.  I suspect it's memory.  That involves some
manual steps.  Inspection didn't yield any obvious mistakes.

I don't have a good strategy to test this apart from going over every
feature and writing or generating a testbench.

Actually, quickcheck..  Does it make sense to generate a random
network?  Most would likely produce junk.

It needs to be fed with random data.  Or a noise generator.




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